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M12L16161A-5T PDF预览

M12L16161A-5T

更新时间: 2024-02-08 11:22:12
品牌 Logo 应用领域
晶豪 - ESMT 动态存储器
页数 文件大小 规格书
27页 568K
描述
512K x 16Bit x 2Banks Synchronous DRAM

M12L16161A-5T 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2,针数:50
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.54
访问模式:DUAL BANK PAGE BURST最长访问时间:4.5 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PDSO-G50
长度:20.95 mm内存密度:16777216 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:50字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

M12L16161A-5T 数据手册

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M12L16161A  
512K x 16Bit x 2Banks Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
JEDEC standard 3.3V power supply  
The M12L16161A is 16,777,216 bits synchro-  
nous high data rate Dynamic RAM organized as  
2 x 524,288 words by 16 bits, fabricated with  
high performance CMOS technology. Synchro-  
nous design allows precise cycle control with the  
use of system clock I/O transactions are possible  
on every clock cycle. Range of operating fre-  
LVTTL compatible with multiplexed address  
Dual banks operation  
MRS cycle with address key programs  
-
-
-
CAS Latency (2 & 3 )  
Burst Length (1, 2, 4, 8 & full page)  
Burst Type (Sequential & Interleave)  
All inputs are sampled at the positive going edge quencies, programmable burst length and pro-  
of the system clock  
Burst Read Single-bit Write operation  
DQM for masking  
grammable latencies allow the same device to be  
useful for a variety of high bandwidth, high  
performance memory system applications.  
Auto & self refresh  
32ms refresh period (2K cycle)  
ORDERING INFORMATION  
Part NO.  
MAX Freq. Interface  
233MHz  
200MHz  
Package  
M12L16161A-4.3T  
M12L16161A-5T  
M12L16161A-5.5T  
M12L16161A-6T  
M12L16161A-7T  
M12L16161A-8T  
183MHz  
166MHz  
50  
TSOP(II)  
LVTTL  
143MHz  
125MHz  
PIN CONFIGURATION (TOP VIEW)  
DD  
SS  
V
1
V
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
DQ0  
DQ1  
2
DQ15  
DQ14  
3
SSQ  
V
SSQ  
V
4
DQ2  
DQ3  
VDDQ  
DQ4  
DQ5  
5
DQ13  
DQ12  
VDDQ  
DQ11  
DQ10  
6
7
8
9
SSQ  
V
SSQ  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
DQ6  
DQ7  
DQ9  
DQ8  
DDQ  
V
DDQ  
V
LDQM  
WE  
CAS  
RAS  
CS  
N.C/RFU  
UDQM  
CLK  
CKE  
N.C  
A9  
BA  
A10/AP  
A0  
A8  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
50PIN TSOP(II)  
(400mil x 825mil)  
(0.8 mm PIN PITCH)  
VDD  
VSS  
:
Publication Da te J an. 2000  
Elite Semiconductor Memory Technology Inc.  
P.1  
:
Revis ion 1.3u  

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