Datasheet > M12L16161A-4.3T

M12L16161A-4.3T

更新时间： 2024-02-18 04:50:27

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
27页	568K
描述
512K x 16Bit x 2Banks Synchronous DRAM

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中文翻译

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数据手册

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M12L16161A-4.3T 数据手册

M12L16161A

512K x 16Bit x 2Banks Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

JEDEC standard 3.3V power supply

The M12L16161A is 16,777,216 bits synchro-

nous high data rate Dynamic RAM organized as

2 x 524,288 words by 16 bits, fabricated with

high performance CMOS technology. Synchro-

nous design allows precise cycle control with the

use of system clock I/O transactions are possible

on every clock cycle. Range of operating fre-

LVTTL compatible with multiplexed address

Dual banks operation

MRS cycle with address key programs

CAS Latency (2 & 3 )

Burst Length (1, 2, 4, 8 & full page)

Burst Type (Sequential & Interleave)

All inputs are sampled at the positive going edge quencies, programmable burst length and pro-

of the system clock

Burst Read Single-bit Write operation

DQM for masking

grammable latencies allow the same device to be

useful for a variety of high bandwidth, high

performance memory system applications.

Auto & self refresh

32ms refresh period (2K cycle)

ORDERING INFORMATION

Part NO.

MAX Freq. Interface

233MHz

200MHz

Package

M12L16161A-4.3T

M12L16161A-5T

M12L16161A-5.5T

M12L16161A-6T

M12L16161A-7T

M12L16161A-8T

183MHz

166MHz

TSOP(II)

LVTTL

143MHz

125MHz

PIN CONFIGURATION (TOP VIEW)

DQ0

DQ1

DQ15

DQ14

SSQ

DQ2

DQ3

VDDQ

DQ4

DQ5

DQ13

DQ12

VDDQ

DQ11

DQ10

SSQ

DQ6

DQ7

DQ9

DQ8

DDQ

LDQM

CAS

RAS

N.C/RFU

UDQM

CLK

CKE

N.C

A10/AP

50PIN TSOP(II)

(400mil x 825mil)

(0.8 mm PIN PITCH)

VDD

VSS

Publication Da te J an. 2000

Elite Semiconductor Memory Technology Inc.

P.1

Revis ion 1.3u

12 3 4 5 6 7...27

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