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M12L128168A-6BIG PDF预览

M12L128168A-6BIG

更新时间: 2024-01-19 00:05:59
品牌 Logo 应用领域
晶豪 - ESMT 存储内存集成电路动态存储器
页数 文件大小 规格书
22页 361K
描述
2M x 16 Bit x 4 Banks Synchronous DRAM

M12L128168A-6BIG 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
零件包装代码:TSOP2包装说明:TSOP2, TSOP54,.46,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.25访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):166 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
长度:22.22 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.002 A
子类别:DRAMs最大压摆率:0.16 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

M12L128168A-6BIG 数据手册

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ESMT  
M12L128168A  
Operation temperature condition -40°C ~85°C  
SDRAM  
2M x 16 Bit x 4 Banks  
Synchronous DRAM  
FEATURES  
ORDERING INFORMATION  
y
y
y
y
JEDEC standard 3.3V power supply  
LVTTL compatible with multiplexed address  
Four banks operation  
MRS cycle with address key programs  
- CAS Latency ( 2 & 3 )  
- Burst Length ( 1, 2, 4, 8 & full page )  
- Burst Type ( Sequential & Interleave )  
All inputs are sampled at the positive going edge of the  
system clock  
Burst Read single write operation  
DQM for masking  
PRODUCT NO.  
M12L128168A-5TIG  
M12L128168A-5BIG  
M12L128168A-6TIG  
M12L128168A-6BIG  
M12L128168A-7TIG  
M12L128168A-7BIG  
MAX FREQ. PACKAGE COMMENTS  
200MHz  
200MHz  
166MHz  
166MHz  
143MHz  
143MHz  
TSOP II  
BGA  
Pb-free  
Pb-free  
Pb-free  
Pb-free  
Pb-free  
Pb-free  
TSOP II  
BGA  
y
TSOP II  
BGA  
y
y
y
y
Auto & self refresh  
64ms refresh period (4K cycle)  
GENERAL DESCRIPTION  
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.  
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  
variety of high bandwidth, high performance memory system applications.  
Pin Arrangement (Top View)  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
VSS  
1
2
3
4
5
6
7
8
9
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
VSSQ  
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
VSSQ  
DQ7  
VDD  
1
DQ15  
VSSQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VDDQ  
DQ8  
VSS  
2
VSSQ  
VDDQ  
DQ0  
VDD  
A
B
C
D
E
F
VSS  
DQ15  
3
4
5
VDDQ  
VSSQ  
VSSQ  
VDDQ  
DQ2  
DQ4  
DQ1  
DQ3  
DQ14  
DQ12  
DQ13  
DQ11  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
VSSQ  
VDD  
DQ6  
DQ10  
DQ8  
DQ9  
NC  
VDDQ  
VSS  
DQ5  
DQ7  
LDQM  
NC  
LDQM  
WE  
UDQM  
CLK  
CKE  
NC  
UDQM  
NC  
CLK  
A11  
CKE  
A9  
CAS  
A13  
RAS  
A12  
WE  
CS  
CAS  
RAS  
CS  
G
H
J
A11  
A13  
A9  
A12  
A8  
A10/AP  
A0  
A8  
A0  
A3  
A10  
A7  
A5  
A6  
A4  
A1  
A2  
A7  
A6  
A1  
VSS  
VDD  
A5  
A2  
A4  
A3  
VSS  
VDD  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Oct. 2007  
Revision: 1.2 1/43  

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