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M12L128168A-6BG2L PDF预览

M12L128168A-6BG2L

更新时间: 2024-02-17 17:00:44
品牌 Logo 应用领域
晶豪 - ESMT 存储内存集成电路动态存储器
页数 文件大小 规格书
45页 688K
描述
ABSOLUTE MAXIMUM RATINGS

M12L128168A-6BG2L 技术参数

生命周期:Contact Manufacturer包装说明:VFBGA,
Reach Compliance Code:unknown风险等级:5.62
访问模式:FOUR BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:S-PBGA-B54
长度:8 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:SQUARE
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH座面最大高度:1 mm
自我刷新:YES最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:8 mmBase Number Matches:1

M12L128168A-6BG2L 数据手册

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ESMT  
SDRAM  
M12L128168A (2L)  
2M x 16 Bit x 4 Banks  
Synchronous DRAM  
FEATURES  
ORDERING INFORMATION  
y
y
y
y
JEDEC standard 3.3V power supply  
LVTTL compatible with multiplexed address  
Four banks operation  
MRS cycle with address key programs  
- CAS Latency ( 2 & 3 )  
- Burst Length ( 1, 2, 4, 8 & full page )  
- Burst Type ( Sequential & Interleave )  
All inputs are sampled at the positive going edge of the  
system clock  
Burst Read single write operation  
DQM for masking  
Product ID  
Max Freq.  
Package  
Comments  
Pb-free  
Pb-free  
Pb-free  
Pb-free  
Pb-free  
Pb-free  
M12L128168A-5TG2L 200MHz 54 Pin TSOP II  
M12L128168A-5BG2L 200MHz 54 Ball FBGA  
M12L128168A-6TG2L 166MHz 54 Pin TSOP II  
M12L128168A-6BG2L 166MHz 54 Ball FBGA  
M12L128168A-7TG2L 143MHz 54 Pin TSOP II  
M12L128168A-7BG2L 143MHz 54 Ball FBGA  
y
y
y
y
y
Auto & self refresh  
64ms refresh period (4K cycle)  
GENERAL DESCRIPTION  
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.  
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  
variety of high bandwidth, high performance memory system applications.  
PIN CONFIGURATION (TOP VIEW)  
BALL CONFIGURATION (TOP VIEW)  
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)  
(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jun. 2012  
Revision: 1.3  
1/45  

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ABSOLUTE MAXIMUM RATINGS
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