Datasheet > M12L128168A-5BG2S

M12L128168A-5BG2S

更新时间： 2024-09-24 21:13:39

品牌	Logo	应用领域
晶豪 - ESMT		动态存储器
页数	文件大小	规格书
45页	789K
描述
DRAM,

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中文翻译

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技术参数
数据手册

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M12L128168A-5BG2S 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.62
Base Number Matches：	1

M12L128168A-5BG2S 数据手册

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ESMT

SDRAM

M12L128168A (2S)

2M x 16 Bit x 4 Banks

Synchronous DRAM

FEATURES

ORDERING INFORMATION

JEDEC standard 3.3V power supply

LVTTL compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

- CAS Latency ( 2 & 3 )

- Burst Length ( 1, 2, 4, 8 & full page )

- Burst Type ( Sequential & Interleave )

All inputs are sampled at the positive going edge of the

system clock

Burst Read single write operation

DQM for masking

Max

Product ID

Package

Comments

Freq.

M12L128168A-5TG2S

M12L128168A-5BG2S

M12L128168A-6TG2S

M12L128168A-6BG2S

M12L128168A-7TG2S

M12L128168A-7BG2S

200MHz 54 Pin TSOPII Pb-free

200MHz 54 Ball FBGA Pb-free

166MHz 54 Pin TSOPII Pb-free

166MHz 54 Ball FBGA Pb-free

143MHz 54 Pin TSOPII Pb-free

143MHz 54 Ball FBGA Pb-free

Auto & self refresh

64ms refresh period (4K cycle)

GENERAL DESCRIPTION

The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system applications.

PIN CONFIGURATION (TOP VIEW)

BALL CONFIGURATION (TOP VIEW)

(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)

(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2017

Revision: 1.0

1/45

12 3 4 5 6 7...45

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与M12L128168A-5BG2S相关器件

型号	品牌	获取价格	描述	数据表
M12L128168A-5BIG	ESMT	获取价格	2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-5BIG2L	ESMT	获取价格	Synchronous DRAM, 8MX16, 4.5ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD F
M12L128168A-5BIG2N	ESMT	获取价格	Synchronous DRAM, 8MX16, 5ns, CMOS, PBGA54, 8 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FRE
M12L128168A-5T	ESMT	获取价格	2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-5TG	ESMT	获取价格	2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-5TG2L	ESMT	获取价格	ABSOLUTE MAXIMUM RATINGS
M12L128168A-5TG2N	ESMT	获取价格	暂无描述
M12L128168A-5TG2S	ESMT	获取价格	暂无描述
M12L128168A-5TIG	ESMT	获取价格	2M x 16 Bit x 4 Banks Synchronous DRAM
M12L128168A-5TIG2L	ESMT	获取价格	Synchronous DRAM, 8MX16, 4.5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE