Datasheet > M1020-13I172.6423LF

M1020-13I172.6423LF

更新时间： 2023-01-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	440K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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P r o d u c t D a t a S h e e t

Integrated

Circuit

Systems, Inc.

M1020/21

VCSO BASED CLOCK PLL

GENERAL DESCRIPTION

PIN ASSIGNMENT (9 x 9 mm SMT)

The M1020/21 is a VCSO (Voltage Controlled SAW

Oscillator) based clock jitter

attenuator PLL designed for clock

jitter attenuation and frequency

translation. The device is ideal for

generating the transmit reference

clock for optical network systems

supporting up to 2.5Gb data rates.

It can serve to jitter attenuate a

MR_SEL2

MR_SEL0

MR_SEL1

LOL

P_SEL0

P_SEL1

nFOUT0

FOUT0

GND

nFOUT1

FOUT1

VCC

M1020

M1021

NBW

VCC

stratum reference clock or a recovered clock in loop

timing mode. The M1020/21 module includes a

proprietary SAW (surface acoustic wave) delay line as

part of the VCSO. This results in a high frequency,

high-Q, low phase noise oscillator that assures low

intrinsic output jitter.

( T o p V i e w )

DNC

GND

FEATURES

◆ Integrated SAW delay line; low phase jitter of < 0.5ps

rms, typical (12kHz to 20MHz)

Figure 1: Pin Assignment

◆ Output frequencies of 62.5 to 175 MHz

Example I/O Clock Frequency Combinations

Using M1020-11-155.5200 or M1021-11-155.5200

(Specify VCSO output frequency at time of order)

◆ LVPECL clock output (CML and LVDS options available)

◆ Reference clock inputs support differential LVDS,

PLL Ratio

Output Clock

Input Reference

Clock (MHz)

LVPECL, as well as single-ended LVCMOS, LVTTL

(Pin Selectable)

(MHz)

(Pin Selectable)

◆ Loss of Lock (LOL) output pin

(M1020)

(M1021)

(M1020) (M1021)

◆ Narrow Bandwidth control input (NBW pin)

19.44 or 38.88

8 or 4

155.52

77.76

◆ Hitless Switching (HS) options with or without Phase

Build-out (PBO) to enable SONET (GR-253) / SDH

(G.813) MTIE and TDEV compliance during reselection

77.76

155.52

622.08

0.25

◆ Pin-selectable feedback and reference divider ratios

◆ Industrial temperature grade available

◆ Single 3.3V power supply

Table 1: Example I/O Clock Frequency Combinations

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop

Filter

M1020/21

NBW

LOL

MUX

Phase

Detector

DIF_REF0

nDIF_REF0

R Div

VCSO

DIF_REF1

nDIF_REF1

M Divider

REF_SEL

M/R Divider

LUT

MR_SEL3:0

FOUT0

nFOUT0

P Divider

TriState

(1, 2, or TriState)

FOUT1

nFOUT1

P Divider

LUT

P_SEL1:0

Figure 2: Simplified Block Diagram

M1020/21 Datasheet Rev 1.0

Revised 28Jul2004

M1020/21 VCSO Based Clock PLL

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7...10

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