Datasheet > M1020-11I155.5200

M1020-11I155.5200

更新时间： 2024-11-05 15:38:35

品牌	Logo	应用领域
艾迪悌 - IDT		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
10页	305K
描述
CLCC-36, Tube

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M1020-11I155.5200 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	CLCC
包装说明：	QCCN,	针数：	36
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.78	应用程序：	SONET;SDH
JESD-30 代码：	S-CQCC-N36	JESD-609代码：	e0
长度：	8.99 mm	功能数量：	1
端子数量：	36	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	3.1 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	NO LEAD
端子节距：	0.635 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	8.99 mm
Base Number Matches：	1

M1020-11I155.5200 数据手册

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P r o d u c t D a t a S h e e t

Integrated

Circuit

Systems, Inc.

M1020/21

VCSO BASED CLOCK PLL

GENERAL DESCRIPTION

PIN ASSIGNMENT (9 x 9 mm SMT)

The M1020/21 is a VCSO (Voltage Controlled SAW

Oscillator) based clock jitter

attenuator PLL designed for clock

jitter attenuation and frequency

translation. The device is ideal for

generating the transmit reference

clock for optical network systems

supporting up to 2.5Gb data rates.

It can serve to jitter attenuate a

MR_SEL2

MR_SEL0

MR_SEL1

LOL

P_SEL0

P_SEL1

nFOUT0

FOUT0

GND

nFOUT1

FOUT1

VCC

M1020

M1021

NBW

VCC

stratum reference clock or a recovered clock in loop

timing mode. The M1020/21 module includes a

proprietary SAW (surface acoustic wave) delay line as

part of the VCSO. This results in a high frequency,

high-Q, low phase noise oscillator that assures low

intrinsic output jitter.

( T o p V i e w )

DNC

GND

FEATURES

◆ Integrated SAW delay line; low phase jitter of < 0.5ps

rms, typical (12kHz to 20MHz)

Figure 1: Pin Assignment

◆ Output frequencies of 62.5 to 175 MHz

Example I/O Clock Frequency Combinations

Using M1020-11-155.5200 or M1021-11-155.5200

(Specify VCSO output frequency at time of order)

◆ LVPECL clock output (CML and LVDS options available)

◆ Reference clock inputs support differential LVDS,

PLL Ratio

Output Clock

Input Reference

Clock (MHz)

LVPECL, as well as single-ended LVCMOS, LVTTL

(Pin Selectable)

(MHz)

(Pin Selectable)

◆ Loss of Lock (LOL) output pin

(M1020)

(M1021)

(M1020) (M1021)

◆ Narrow Bandwidth control input (NBW pin)

19.44 or 38.88

8 or 4

155.52

77.76

◆ Hitless Switching (HS) options with or without Phase

Build-out (PBO) to enable SONET (GR-253) / SDH

(G.813) MTIE and TDEV compliance during reselection

77.76

155.52

622.08

0.25

◆ Pin-selectable feedback and reference divider ratios

◆ Industrial temperature grade available

◆ Single 3.3V power supply

Table 1: Example I/O Clock Frequency Combinations

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop

Filter

M1020/21

NBW

LOL

MUX

Phase

Detector

DIF_REF0

nDIF_REF0

R Div

VCSO

DIF_REF1

nDIF_REF1

M Divider

REF_SEL

M/R Divider

LUT

MR_SEL3:0

FOUT0

nFOUT0

P Divider

TriState

(1, 2, or TriState)

FOUT1

nFOUT1

P Divider

LUT

P_SEL1:0

Figure 2: Simplified Block Diagram

M1020/21 Datasheet Rev 1.0

Revised 28Jul2004

M1020/21 VCSO Based Clock PLL

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7...10

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与M1020-11I155.5200相关器件

型号	品牌	获取价格	描述	数据表
M1020-11I155.5200T	IDT	获取价格	CLCC-36, Reel
M1020-11I155.52LFT	IDT	获取价格	CLCC-36, Reel
M1020-11I156.2500LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M1020-11I166.6286LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M1020-11I167.2820	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M1020-11I167.2820LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M1020-11I167.3280LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M1020-11I168.0400LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M1020-11I172.6423LF	IDT	获取价格	Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36
M1020-11I175.0000	IDT	获取价格	PLL/Frequency Synthesis Circuit

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