Datasheet > M02050-15EVM

M02050-15EVM

更新时间： 2022-02-26 12:20:23

品牌	Logo	应用领域
泰科 - TE		/
页数	文件大小	规格书
28页	740K
描述
3.3/5V Limiting Amplifier for Applications to 2.5 Gbps

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M02050-15EVM 数据手册

M02050-15

3.3/5V Limiting Amplifier for Applications to 2.5 Gbps

The M02050-15 is an integrated high-gain limiting amplifier. The M02050-15 features PECL outputs and is intended

for use in applications to 2.5 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02050-15

can operate with a 3.3V or 5V supply.

Rate select is supported for SFP applications and/or to achieve optimum sensitivity at data rates ≤ 1.25 Gbps.

When rate select is high, optimum sensitivity is achieved at 2.5 Gbps.

The M02050-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input sig-

nal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are

enabled.

Other available solutions: M02049-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)

M02040-15 3.3/5V Limiting Amplifier for Applications to 2.125 Gbps (PECL outputs)

M02043-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)

1.25 Gbps and 4.25 Gbps SFP reference designs available on Mindspeed.com

Applications

Features

• 2.5 Gbps STM-16/OC-48 SDH/SONET

• 1.06, 2.12 and 4.24 Gbps Fibre Channel

• 1.25 Gbps Ethernet

• Operates with a 3.3V or 5V supply

• 3.5 mV typical input sensitivity at 2.5 Gbps

• PECL outputs

• 1.25 Gbps SDH/SONET

• Rate Selection for ≤ 1.25 Gbps operation

• 2.67 Gbps SDH/SONET with FEC

• Average Receive power monitor output (RSSI_AVG

• Peak-to-peak Receive power monitor output (RSSI_PP

• On-chip DC offset cancellation circuit

• Low power (< 180 mW at 3.3V)

)

• Output Jam Function

• 16 pin 3x3 QFN package

Typical Applications Diagram

12.1 kΩ

Jam

optional

RATE

Control

SEL

RATE

REF

SEL

+3.3 V

Biasing

AC-Coupled

to TIA

DINP

PECLP

PECLN

Clock Data

Recovery

Unit

Limiting

Amplifier

Output

Buffer

MT02I0A13

Photodiode

DINN

MON

Offset cancel

Level

Detect

RSSI

AC or DC Coupled

(as described in

Comparator

RxAVG

Level

Shift

Threshold

Setting

Circuit

Applications Information)

Regulator

LOS

RSSI

AVG

EXT

SET

CC3 CC

02050-DSH-002-F

Mindspeed Technologies™

Mindspeed Proprietary and Confidential

August 2005

12 3 4 5 6 7...28

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