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LXT336QE PDF预览

LXT336QE

更新时间: 2024-11-24 23:48:59
品牌 Logo 应用领域
其他 - ETC 电信集成电路PC
页数 文件大小 规格书
22页 256K
描述
PCM RECEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|64PIN|PLASTIC

LXT336QE 数据手册

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LXT336  
Quad T1/E1 Receiver  
Datasheet  
The LXT336 quad receiver is a fully-integrated, quadruple-PCM receiver for both T1 (1.544  
Mbps) and E1 (2.048 Mbps) applications. It incorporates four independent receivers in a single  
64-pin QFP package.  
The LXT336 features a differential receiver architecture with high noise interference margin. It  
uses peak detection with a variable threshold for reliable recovery of data as low as 500 mV and  
up to 12 dB of cable attenuation.  
The fully digital clock recovery system uses a low frequency master clock of 2.048 MHz or  
1.544 MHz as its reference. In addition, each LXT336 receiver incorporates a Loss of Signal  
(LOS) detection circuit. The LOS detector is compliant with both ITU-T G.775 and ANSI  
T1.231 standards.  
The LXT336 ports can be independently configured for either unipolar or bipolar output modes.  
HDB3 and AMI decoding mechanisms are available in unipolar mode.  
Applications  
Test Equipment  
High density T1/E1 line cards  
DSX-1 and E1 Line Monitoring  
Product Features  
Fully integrated quad, receiver for E1 2.048 Low frequency 1.544 or 2.048 MHz  
Mbps or T1 1.544 Mbps operation  
reference clock  
Single rail supply voltage of 5 V (typical)  
Programmable unipolar and bipolar PCM  
interface  
Low power consumption: 250 mW for E1;  
200 mW for T1 (typical)  
On-chip AMI and HDB3 decoders  
High-performance receivers recover data  
Loss of Signal processors conform to ITU  
with up to 12 dB cable attenuation  
G.775 and ANSI T1.231 recommendations  
On-chip clock recovery function complies Small-footprint 64-pin QFP  
with ITU G.823 and Bellcore GR-499-  
CORE  
Optional RZ Data recovery mode  
As of January 15, 2001, this document replaces the Level One document  
LXT336 — Quad T1/E1 Receiver.  
Order Number: 249046-001  
January 2001  

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