Datasheet > LTC6957-3_15

LTC6957-3_15

更新时间： 2024-11-16 01:09:27

品牌	Logo	应用领域
凌特 - Linear		/
页数	文件大小	规格书
36页	1390K
描述
Low Phase Noise, Dual Output Buffer/Driver/ Logic Converter

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数据手册

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LTC6957-3_15 数据手册

LTC6957-1/LTC6957-2/

LTC6957-3/LTC6957-4

Low Phase Noise, Dual

Output Buffer/Driver/

Logic Converter

FeaTures

DescripTion

Low Phase Noise Buffer/Driver

The LTC^®6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is

a family of very low phase noise, dual output AC signal

buffer/driver/logic level translators. The input signal can

Optimized Conversion of Sine Wave Signals to

Logic Levels

be a sine wave or any logic level (≤2V ). There are four

Three Logic Output Types Available

P-P

members of the family that differ in their output logic

signal type as follows:

– LVPECL

– LVDS

– CMOS

Additive Jitter 45fs

LTC6957-1: LVPECL Logic Outputs

(LTC6957-1)

RMS

LTC6957-2: LVDS Logic Outputs

Frequency Range Up to 300MHz

3.15V to 3.45V Supply Operation

Low Skew 3ps Typical

Fully Specified from –40°C to 125°C

12-Lead MSOP and 3mm × 3mm DFN Packages

LTC6957-3: CMOS Logic, In-Phase Outputs

LTC6957-4: CMOS Logic, Complementary Outputs

The LTC6957 will buffer and distribute any logic signal

with minimal additive noise, however, the part really ex-

cels at translating sine wave signals to logic levels. The

early amplifier stages have selectable lowpass filtering

to minimize the noise while still amplifying the signal to

increaseitsslewrate. Thisinputstagefiltering/noiselimit-

ing is especially helpful in delivering the lowest possible

phase noise signal with slow slewing input signals such

as a typical 10MHz sine wave system reference.

applicaTions

System Reference Frequency Distribution

High Speed ADC, DAC, DDS Clock Driver

Military and Secure Radio

Low Noise Timing Trigger

Broadband Wireless Transceiver

High Speed Data Acquisition

Medical Imaging

Test and Measurement

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents 7969189 and 8319551.

Typical applicaTion

3.3V

0.1µF

Additive Phase Noise at 100MHz

–140

SINGLE-ENDED SINE WAVE INPUT

AT +7dBm (500mV

)

RMS

SD1

FILTA = FILTB = GND

FILTA

–145

–150

–155

–160

–165

FILTB

TO PLL CHIPS

OR SYSTEM

SAMPLING CLOCKS

OUT1

100MHz

LTC6957-2 (LVDS)

LTC6957-4 (CMOS)

+7dBm

10nF

–

SINE WAVE

OCXO

50Ω

10nF

OUT2

LTC6957-3

(CMOS)

GND

SD2

LTC6957-1 (LVPECL)

1k 10k

OFFSET FREQUENCY (Hz)

6957 TA01a

100

100k

69571234 TA01b

6957f

For more information www.linear.com/LTC6957-1

12 3 4 5 6 7...36

中文翻译

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与LTC6957-3_15相关器件

型号	品牌	获取价格	描述	数据表
LTC6957-4	Linear	获取价格	280MHz, 2.9ns Comparator Family with Rail-to-Rail Inputs and CMOS Outputs
LTC6957-4	ADI	获取价格	Low Phase Noise, Dual Output Logic Converter
LTC6957-4_15	Linear	获取价格	Low Phase Noise, Dual Output Buffer/Driver/ Logic Converter
LTC695C	Linear	获取价格	Microprocessor Supervisory Circuits
LTC695C-3.3	Linear	获取价格	3.3V Microprocessor Supervisory Circuits
LTC695CJ	Linear	获取价格	IC 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, CDIP16, 0.300 INCH, HERMETIC SEALED, CERDIP-16,
LTC695CN	Linear	获取价格	Microprocessor Supervisory Circuits
LTC695CN#PBF	Linear	获取价格	LTC695 - Microprocessor Supervisory Circuits; Package: PDIP; Pins: 16; Temperature Range:
LTC695CN-3.3	Linear	获取价格	3.3V Microprocessor Supervisory Circuits
LTC695CN-3.3#PBF	Linear	获取价格	LTC695-3.3 - 3.3V Microprocessor Supervisory Circuits; Package: PDIP; Pins: 16; Temperatur

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