LTC6955
Ultralow Jitter, 7.5GHz,
11 Output Fanout
Buffer Family
FEATURES
DESCRIPTION
The LTC®6955 is a high performance, ultralow jitter,
fanout clock buffer with eleven outputs. Its 4-pin parallel
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LTC6955: 11 Output Buffer
LTC6955-1: 10 Buffered Outputs and One ÷2 Output
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Additive Output Jitter ~45fs RMS (ADC SNR Method) control port allows for multiple output setups, enabling
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Additive Output Jitter < 5fs RMS
any number between three and eleven outputs, as well as
a complete shutdown. The parallel port also provides the
ability to invert the output polarity of alternating outputs,
simplifying designs with top and bottom board routing.
Each of the CML outputs can run from DC to 7.5GHz.
The LTC6955-1 replaces one output buffer with a divide-
by-2 frequency divider, allowing it to drive Analog Devices’
LTC6952 or LTC6953 to generate JESD204B subclass 1
SYSREF signals. These SYSREFs can pair with ultralow
jitter device clocks from the LTC6955-1, which can run
at frequencies up to 7.5GHz.
(Integration BW = 12kHz to 20MHz, f = 7.5GHz)
Eleven Ultralow Noise CML Outputs
Parallel Control for Multiple Output Configurations
–40°C to 125°C Operating Junction Temperature
Range
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APPLICATIONS
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High Performance Data Converter Clocking
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SONET, Fibre Channel, GigE Clock Distribution
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Low Skew and Jitter Clock and Data Fanout
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 8319551 and 8819472.
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Wireless and Wired Communications
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Single-Ended to Differential Conversion
TYPICAL APPLICATION
7GHz Cumulative Phase Noise
ADF4371 Driving LTC6955
Generation of Multiple Low Jitter 7GHz Clocks
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