Datasheet > LTC5557

LTC5557

更新时间： 2022-11-16 12:28:00

品牌	Logo	应用领域
凌特 - Linear		/
页数	文件大小	规格书
28页	893K
描述
16-Bit, 125/105/80Msps Low Power Dual ADCs Serial SPI Port for Configuration

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LTC5557 数据手册

LTC2195

LTC2194/LTC2193

16-Bit, 125/105/80Msps

Low Power Dual ADCs

FEATURES

DESCRIPTION

The LTC^®2195/LTC2194/LTC2193 are 2-channel, simul-

taneous sampling 16-bit A/D converters designed for

digitizing high frequency, wide dynamic range signals.

They are perfect for demanding communications applica-

tions with AC performance that includes 76.8dB SNR and

90dB spurious free dynamic range (SFDR). Ultralow jitter

2-Channel Simultaneous Sampling ADC

Serial LVDS Outputs: 1, 2 or 4 Bits per Channel

76.8dB SNR

90dB SFDR

Low Power: 432mW/360mW/249mW Total

216mW/180mW/125mW per Channel

Single 1.8V Supply

of0.07ps

allowsundersamplingofIFfrequencieswith

RMS

Selectable Input Ranges: 1V to 2V

excellent noise performance.

P-P

550MHz Full-Power Bandwidth S/H

DC specs include 2LSB INL (typ), 0.5LSB DNL (typ)

and no missing codes over temperature. The transition

Shutdown and Nap Modes

Serial SPI Port for Conﬁguration

52-Pin (7mm × 8mm) QFN Package

noise is 3.4LSB

RMS

To minimize the number of data lines the digital outputs

are serial LVDS. Each channel outputs two bits or four bits

at a time. At lower sampling rates there is a one bit per

channel option. The LVDS drivers have optional internal

termination and adjustable output levels to ensure clean

signal integrity.

APPLICATIONS

Communications

Cellular Base Stations

Software-Deﬁned Radios

Portable Medical Imaging

Multi-Channel Data Acquisition

–

The ENC and ENC inputs may be driven differentially or

single ended with a sine wave, PECL, LVDS, TTL or CMOS

inputs. An internal clock duty cycle stabilizer allows high

performance at full speed for a wide range of clock duty

cycles.

Nondestructive Testing

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

2-Tone FFT, f_IN= 70MHz and 69MHz

1.8V

–10

–20

–30

–40

–50

OUT1A

OUT1B

OUT1C

OUT1D

OUT2A

OUT2B

OUT2C

OUT2D

CH1

ANALOG

INPUT

16-BIT

ADC CORE

S/H

CH2

ANALOG

INPUT

SERIALIZED

16-BIT

ADC CORE

DATA

SERIALIZER

–60

LVDS

–70

OUTPUTS

–80

–90

–100

–110

–120

ENCODE

INPUT

PLL

DATA CLOCK OUT

FRAME

GND

OGND

219543 TA01a

FREQUENCY (MHz)

219543 TA01b

219543f

12 3 4 5 6 7...28

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