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LTC3831

更新时间： 2024-09-27 14:57:27
品牌 Logo 应用领域
亚德诺 - ADI 开关双倍数据速率控制器存储
页数 文件大小 规格书
20页 213K
描述
用于 DDR 存储器终端的高功率同步开关稳压控制器

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中文翻译

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LTC3831 数据手册

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LTC3831  
High Power Synchronous  
Switching Regulator Controller  
for DDR Memory Termination  
DESCRIPTION  
FEATURES  
The LTC®3831 is a high power, high efficiency switching  
regulator controller designed for DDR memory termina-  
tion. The LTC3831 generates an output voltage equal  
to 1/2 of an external supply or reference voltage. The  
LTC3831 uses a synchronous switching architecture  
with N-channel MOSFETs. Additionally, the chip senses  
output current through the drain-source resistance of the  
upperN-channelFET,providinganadjustablecurrentlimit  
without a current sense resistor.  
n
High Power Switching Regulator Controller  
for DDR Memory Termination  
OUT  
n
V
Tracks 1/2 of V or External V  
IN REF  
n
n
n
n
n
n
No Current Sense Resistor Required  
Low Input Supply Voltage Range: 3V to 8V  
Maximum Duty Cycle >91% Over Temperature  
Drives All N-Channel External MOSFETs  
High Efficiency: Over 95% Possible  
Programmable Fixed Frequency Operation:  
100kHz to 500kHz  
The LTC3831 operates with input supply voltage as low as  
3V and with a maximum duty cycle of >91%. It includes  
a fixed frequency PWM oscillator for low output ripple  
operation. The 200kHz free-running clock frequency can  
be externally adjusted or synchronized with an external  
signal from 100kHz to above 500kHz. In shutdown mode,  
the LTC3831 supply current drops to <10μA.  
n
n
n
n
n
External Clock Synchronization Operation  
Programmable Soft-Start  
Low Shutdown Current: <10μA  
Overtemperature Protection  
Available in 16-Pin Narrow SSOP Package  
APPLICATIONS  
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
n
DDR SDRAM Termination  
n
SSTL_2 Interface  
n
SSTL_3 Interface  
TYPICAL APPLICATION  
V
DDQ  
2.5V  
5V  
Efficiency vs Load Current  
100  
+
C
IN  
MBR0530T1  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
330μF  
×2  
0.1μF  
1k  
1μF  
PV  
PV  
Q1  
MBRS340T3  
10k  
CC2  
CC1  
TG  
V
CC  
0.1μF  
L
O
0.1μF  
SS  
I
MAX  
1.2μH  
V
TT  
0.01μF  
130k  
+
1.25V  
6A  
LTC3831  
I
FB  
4.7μF  
Q2  
MBRS340T3  
FREQSET  
SHDN  
BG  
PGND  
GND  
+
C
OUT  
470μF  
SHDN  
T
V
V
= 25°C  
A
= 2.5V  
IN  
OUT  
COMP  
×3  
C
: SANYO POSCAP 6TPB330M  
C : SANYO POSCAP 4TPB470M  
OUT  
Q1, Q2: SILICONIX Si4410DY  
IN  
= 1.25V  
C1  
33pF  
R
+
C
R
15k  
3831 F01  
0
1
3
4
5
6
2
FB  
C
C
–
R
LOAD CURRENT (A)  
1500pF  
2831 G01  
Figure 1. Typical DDR Memory Termination Application  
3831fb  
1
1234567...20

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