LTC3718
Low Input Voltage
DC/DC Controller for
DDR/QDR Memory Termination
U
FEATURES
DESCRIPTIO
The LTC®3718 is a high current, high efficiency synchro-
nous switching regulator controller for DDR and QDRTM
memory termination. It operates from an input as low as
1.5V and provides a regulated output voltage equal to
(0.5)VIN. The controller uses a valley current control
architecture to enable high frequency operation with very
lowon-timeswithoutrequiringasenseresistor.Operating
frequency is selected by an external resistor and is com-
pensatedforvariationsinVIN andVOUT.TheLTC3718uses
a pair of standard 5V logic level N-channel external
MOSFETs, eliminating the need for expensive P-channel
or low threshold devices.
■
Very Low VIN(MIN): 1.5V
■
Ultrafast Transient Response
■
True Current Mode Control
■
5V Drive for N-Channel MOSFETs Eliminates
Auxillary 5V Supply
No Sense Resistor Required
■
■
Uses Standard 5V Logic-Level N-Channel MOSFETs
■
VOUT(MIN): 0.4V
VOUT Tracks 1/2 VIN or External VREF
■
■
Symmetrical Source and Sink Output Current Limit
■
Adjustable Switching Frequency
tON(MIN) <100ns
■
■
Power Good Output Voltage Monitor
Forced continuous operation reduces noise and RF inter-
ference. Fault protection is provided by internal foldback
current limiting, an output overvoltage comparator and an
optional short-circuit timer. Soft-start capability for sup-
ply sequencing can be accomplished using an external
timing capacitor. OPTI-LOOP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
■
Programmable Soft-Start
■
Output Overvoltage Protection
■
Optional Short-Circuit Shutdown Timer
■
Small 24-Lead SSOP Package
U
APPLICATIO S
■
Bus Termination: DDR/QDR Memory, SSTL, HSTL, ...
■
Servers, RAID Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a registered trademark of Linear Technology Corporation. No RSENSE is a
trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a
new family of products developed by Cypress Semiconductor, IDT and Micron Technology, Inc.
■
Distributed Power Systems
Synchronous Buck with General Purpose Boost
■
U
TYPICAL APPLICATIO
V
IN
2.5V
C
IN1
D
B
22µF
CMDSH-3
×2
SHDN
BOOST
C
B
Efficiency vs Load Current
0.33µF
D1
M1
V
TG
REF
B340A
R
Si7440DP
ON
237k
100
90
80
70
60
50
40
30
20
10
0
LTC3718
V
V
= 2.5V
IN
OUT
I
ON
SW1
+
= 1.25V
V
OUT
V
FB1
SENSE
L1 0.8µH
V
OUT
1.25V
PGOOD
RUN/SS
PGND1
C
SS
0.1µF
±10A
–
C
+
OUT
SENSE
470µF
×2
M2
Si7440DP
D2
B340A
BG
C1 820pF X7R
INTV
CC
IN1
IN2
R
4.75k
C
I
V
V
TH
SGND1
V
IN
C
IN2
4.7µF
L2
4.7µH
SGND2
PGND2
SW2
FIGURE 1 CIRCUIT
10 100
V
FB2
0.01
0.1
1
D3
MBR0520
C
VCC1
10µF
LOAD CURRENT (A)
R
12.1k
R
37.4k
F2
F1
3718 G05/TA01a
C
OUT
: SANYO POSCAP 4TPB470M
L1: SUMIDA CEP125-0R8MC
L2: PANASONIC ELJPC4R7MF
3718 TA01
Figure 1. High Efficiency Bus Termination Supply without Auxiliary 5V Supply
3718fa
1
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
