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LTC2655BCGN-H16PBF PDF预览

LTC2655BCGN-H16PBF

更新时间： 2024-09-21 05:43:51
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
28页 357K
描述
Quad I²C 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference

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LTC2655  
2
Quad I C 16-/12-Bit  
Rail-to-Rail DACs with  
10ppm/°C Max Reference  
DESCRIPTION  
FEATURES  
2
The LTC®2655 is a family of Quad I C 16-/12-Bit Rail-to-  
n
Integrated Reference 10ppm/°C Max  
n
Maximum INL Error: ±±LꢀS at 1ꢁ Sitꢂ  
Rail DACs with integrated 10ppm/°C max reference. The  
DACs have built-in high performance, rail-to-rail, output  
buffers and are guaranteed monotonic. The LTC2655-L  
has a full-scale output of 2.5V with the integrated refer-  
ence and operates from a single 2.7V to 5.5V supply.  
The LTC2655-H has a full-scale output of 4.096V with  
the integrated reference and operates from a 4.5V to  
5.5V supply. Each DAC can also operate with an external  
reference, which sets the full-scale output to 2 times the  
external reference voltage.  
n
Guaranteed Monotonic Over Temperature  
n
ꢀelectable Internal or External Reference  
n
2.7V to 5.5V Supply Range (LTC2655-L)  
n
Integrated Reference Buffers  
n
Ultralow Crosstalk Between DACs (<1nV•s)  
n
Power-On-Reset to Zero-Scale/Mid-Scale  
n
Asynchronous DAC Update Pin  
n
Tiny 20-Lead 4mm × 4mm QFN and  
16-Lead Narrow SSOP packages  
2
The parts use the 2-wire I C compatible serial interface.  
The LTC2655 operates in both the standard mode (maxi-  
mum clock rate of 100kHz) and the fast mode (maximum  
clock rate of 400kHz). The LTC2655 incorporates a  
power-on reset circuit that is controlled by the PORSEL  
pin. If PORSEL is tied to GND the DACs power-on reset to  
APPLICATIONS  
n
Mobile Communications  
n
Process Control and Industrial Automation  
n
Instrumentation  
Automatic Test Equipment  
n
zero-scale. If PORSEL is tied to V , the DACs power-on  
CC  
n
Automotive  
reset to mid-scale.  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
Protected by U.S. Patents including 5396245, 6891433 and 7671770.  
BLOCK DIAGRAM  
REFIN/OUT  
REFCOMP  
INTERNAL REFERENCE  
INL Curve  
4
GND  
V
CC  
3
2
REFLO  
V
V
OUTD  
OUTA  
DAC A  
DAC B  
DAC D  
DAC C  
1
0
–1  
–2  
–3  
–4  
V
V
OUTC  
OUTB  
CA0  
CA1  
PORSEL  
SDA  
POWER-ON  
RESET  
128  
16384  
32768  
CODE  
49152  
65535  
32-BIT SHIFT REGISTER  
2-WIRE INTERFACE  
CA2  
SCL  
2655 TA01b  
LDAC  
2655 BD  
2655f  
1
1234567...28

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