LTC2259-16
16-Bit, 80Msps Ultralow
Power 1.8V ADC
FEATURES
DESCRIPTION
The LTC®2259-16 is a sampling 16-bit A/D converter de-
signed for digitizing high frequency, wide dynamic range
signals. It is perfect for demanding communications ap-
plications with AC performance that includes 73.1dB SNR
and 88dB spurious free dynamic range (SFDR). Ultralow
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73.1dB SNR
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88dB SFDR
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Low Power: 89mW
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Single 1.8V Supply
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CMOS, DDR CMOS or DDR LVDS Outputs
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jitterof0.17ps
allowsundersamplingofIFfrequencies
Selectable Input Ranges: 1V to 2V
RMS
P-P
P-P
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with excellent noise performance.
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
DC specs include 4LSB INL (typical) and 0.5LSB DNL
(typical).
The digital outputs can be either full-rate CMOS, double-
data rate CMOS, or double-data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
Serial SPI Port for Configuration
40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
+
–
The ENC and ENC inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
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Communications
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Cellular Base Stations
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Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
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L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
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TYPICAL APPLICATION
1.8V
2-Tone FFT, fIN = 70MHz and 75MHz
0
1.2V
TO 1.8V
V
DD
OV
DD
–10
–20
–30
–40
–50
–60
–70
D15
+
–
16-BIT
PIPELINED
ADC CORE
CMOS
OR
LVDS
•
•
•
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
D0
OGND
–80
–90
CLOCK/DUTY
CYCLE
CONTROL
–100
–110
–120
225916 TA01a
GND
0
20
30
40
10
80MHz
CLOCK
FREQUENCY (MHz)
225916 TA01b
225916f
1