LTC2209
16-Bit, 160Msps ADC
FEATURES
DESCRIPTION
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Sample Rate: 160Msps
TheLTC®2209isa160Msps16-bitA/Dconverterdesigned
for digitizing high frequency, wide dynamic range signals
with input frequencies up to 700MHz. The input range of
the ADC can be optimized with the PGA front end.
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77.3dBFS Noise Floor
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100dB SFDR
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SFDR >84dB at 250MHz (1.5V Input Range)
PGA Front End (2.25V or 1.5V Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
P-P
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P-P
P-P
The LTC2209 is perfect for demanding communications
applications,withACperformancethatincludes77.3dBFS
Noise Floor and 100dB spurious free dynamic range
Optional Data Output Randomizer
LVDS or CMOS Outputs
(SFDR). Ultra low jitter of 70fs
allows undersampling
RMS
ofhighinputfrequencieswithexcellentnoiseperformance.
Maximum DC specs include ±±LSB ꢀNL, ±1LSB DNL (no
missing codes).
Single 3.3V Supply
Power Dissipation: 1.4±W
Clock Duty Cycle Stabilizer
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for
the CMOS outputs: a single bus running at the full data
rate or demultiplexed busses running at half data rate. A
separate output power supply allows the CMOS output
swing to range from 0.±V to 3.6V.
Pin-Compatible Family:
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)
10±Msps: LTC2217 (16-Bit)
64-Pin (9mm × 9mm) QFN Package
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APPLICATIONS
+
–
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
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Telecommunications
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Receivers
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Cellular Base Stations
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Spectrum Analysis
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ꢀmaging Systems
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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ATE
TYPICAL APPLICATION
3.3V
SENSE
64k Point FFT, fIN = 15.1MHz,
–1dBFS, PGA = 0
OV
DD
1.2±V
COMMON MODE
BꢀAS VOLTAGE
ꢀNTERNAL ADC
REFERENCE
GENERATOR
V
0.±V TO 3.6V
0
CM
1μF
–10
2.2μF
–20
OF
CLKOUT
D1±
–30
–40
–±0
–60
–70
+
AꢀN
+
16-BꢀT
PꢀPELꢀNED
ADC CORE
OUTPUT
DRꢀVERS
CORRECTꢀON
LOGꢀC AND
SHꢀFT REGꢀSTER
CMOS
OR
LVDS
ANALOG
ꢀNPUT
S/H
AMP
•
•
•
–
–
AꢀN
D0
–80
–90
OGND
–100
–110
–120
–130
CLOCK/DUTY
CYCLE
CONTROL
3.3V
1μF
V
DD
1μF
1μF
GND
0
10 20 30 40 ±0 60 70 80
2209 TA01
FREQUENCY (MHz)
2209 TA01b
+
–
ENC
ENC
PGA SHDN DꢀTH MODE LVDS RAND
ADC CONTROL ꢀNPUTS
2209fa
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