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LTC2209 PDF预览

LTC2209

更新时间: 2024-11-27 14:57:23
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 597K
描述
16 位、160Msps ADC

LTC2209 数据手册

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LTC2209  
16-Bit, 160Msps ADC  
Features  
Description  
n
Sample Rate: 160Msps  
TheLTC®2209isa160Msps16-bitA/Dconverterdesigned  
for digitizing high frequency, wide dynamic range signals  
with input frequencies up to 700MHz. The input range of  
the ADC can be optimized with the PGA front end.  
n
77.3dBFS Noise Floor  
n
100dB SFDR  
n
SFDR >84dB at 250MHz (1.5V Input Range)  
PGA Front End (2.25V or 1.5V Input Range)  
700MHz Full Power Bandwidth S/H  
Optional Internal Dither  
P-P  
n
n
n
n
n
n
n
n
n
P-P  
P-P  
The LTC2209 is perfect for demanding communications  
applications,withACperformancethatincludes77.3dBFS  
Noise Floor and 100dB spurious free dynamic range  
Optional Data Output Randomizer  
LVDS or CMOS Outputs  
(SFDR). Ultra low jitter of 70fs  
allows undersampling  
RMS  
ofhighinputfrequencieswithexcellentnoiseperformance.  
Maximum DC specs include ±±.±LSB ꢀNL, ±1LSB DNL (no  
missing codes).  
Single 3.3V Supply  
Power Dissipation: 1.±3W  
Clock Duty Cycle Stabilizer  
The digital output can be either differential LVDS or  
single-ended CMOS. There are two format options for  
the CMOS outputs: a single bus running at the full data  
rate or demultiplexed busses running at half data rate. A  
separate output power supply allows the CMOS output  
swing to range from 0.±V to 3.6V.  
Pin-Compatible Family:  
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)  
10±Msps: LTC2217 (16-Bit)  
64-Pin (9mm × 9mm) QFN Package  
n
applications  
+
The ENC and ENC inputs may be driven differentially  
or single-ended with a sine wave, PECL, LVDS, TTL or  
CMOS inputs. An optional clock duty cycle stabilizer al-  
lows high performance at full speed with a wide range of  
clock duty cycles.  
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Telecommunications  
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Receivers  
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Cellular Base Stations  
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Spectrum Analysis  
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ꢀmaging Systems  
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
n
ATE  
typical application  
3.3V  
SENSE  
64k Point FFT, fIN = 15.1MHz,  
–1dBFS, PGA = 0  
OV  
DD  
1.25V  
COMMON MODE  
BIAS VOLTAGE  
INTERNAL ADC  
REFERENCE  
GENERATOR  
V
0.5V TO 3.6V  
1µF  
CM  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
2.2µF  
+
OF  
A
IN  
CLKOUT  
D15  
+
16-BIT  
PIPELINED  
ADC CORE  
OUTPUT  
DRIVERS  
CORRECTION  
LOGIC AND  
SHIFT REGISTER  
CMOS  
OR  
LVDS  
ANALOG  
INPUT  
S/H  
AMP  
A
IN  
D0  
–90  
OGND  
–100  
–110  
–120  
–130  
CLOCK/DUTY  
CYCLE  
CONTROL  
3.3V  
1µF  
V
DD  
1µF  
1µF  
GND  
0
10 20 30 40 50 60 70 80  
2209 TA01  
FREQUENCY (MHz)  
2209 TA01b  
+
ENC  
ENC  
PGA SHDN DITH MODE LVDS RAND  
ADC CONTROL INPUTS  
2209fb  
1

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