LTC2208
16-Bit, 130Msps ADC
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FEATURES
DESCRIPTIO
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Sample Rate: 130Msps
The LTC®2208 is a 130Msps, sampling 16-bit A/D con-
verterdesignedfordigitizinghighfrequency,widedynamic
range signals with input frequencies up to 700MHz. The
input range of the ADC can be optimized with the PGA
front end.
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78dBFS Noise Floor
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100dB SFDR
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SFDR >83dB at 250MHz (1.5V Input Range)
PGA Front End (2.25V or 1.5V Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 1.25W
Clock Duty Cycle Stabilizer
Pin Compatible 1±-Bit Version
130Msps: LTC2208 (16-Bit), LTC2208-1± (1±-Bit)
6±-Pin (9mm × 9mm) QFN Package
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P-P
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P-P
P-P
The LTC2208 is perfect for demanding communications
applications, with AC performance that includes 78dBFS
Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low jitter of 70fs
allows undersampling
RMS
ofhighinputfrequencieswithexcellentnoiseperformance.
Maximum DC specs include ±±LSB ꢀNL, ±1LSB DNL (no
missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
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APPLICATIO S
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Telecommunications
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Receivers
+
–
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Cellular Base Stations
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
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Spectrum Analysis
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ꢀmaging Systems
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ATE
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
3.3V
SENSE
64k Point FFT, F = 15.1MHz,
IN
–1dB, PGA = 0
OV
DD
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
V
0.5V TO 3.6V
1µF
CM
0
–10
2.2µF
–20
–30
–40
–50
–60
–70
–80
OF
CLKOUT
D15
+
AIN
+
16-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
CORRECTION
LOGIC AND
SHIFT REGISTER
CMOS
OR
LVDS
ANALOG
INPUT
S/H
AMP
•
•
•
–
–
AIN
D0
–90
OGND
–100
–110
–120
–130
CLOCK/DUTY
CYCLE
CONTROL
3.3V
1µF
V
DD
1µF
1µF
GND
2208 TA01
0
10
20
30
40
50
60
FREQUENCY (MHz)
+
–
2208 G03
ENC
ENC
PGA SHDN DITH MODE LVDS RAND
ADC CONTROL INPUTS
2208fa
1