LTC2208-14
14-Bit, 130Msps ADC
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FEATURES
DESCRIPTIO
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Sample Rate: 130Msps
The LTC®2208-14 is a 130Msps, sampling 14-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals with input frequencies up to
700MHz. The input range of the ADC can be optimized
with the PGA front end.
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77.1dBFS Noise Floor
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98dB SFDR
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SFDR >81dB at 250MHz (1.5V Input Range)
PGA Front End (2.25V or 1.5V Input Range)
P-P
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P-P
P-P
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 1.32W
Clock Duty Cycle Stabilizer
Pin Compatible 16-Bit Version
130Msps: LTC2208 (16-Bit)
64-Pin (9mm × 9mm) QFN Package
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TheLTC2208-14isperfectfordemandingcommunications
applications,withACperformancethatincludes77.1dBFS
NoiseFloorand98dBspuriousfreedynamicrange(SFDR).
Ultralow jitter of 70fs
allows undersampling of high
RMS
input frequencies with excellent noise performance.
Maximum DC specs include 1.ꢀLSB ꢁNL, 0.ꢀLSB DNL
(no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.ꢀV to 3.6V.
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APPLICATIO S
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Telecommunications
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Receivers
+
–
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Cellular Base Stations
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
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Spectrum Analysis
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ꢁmaging Systems
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ATE
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
3.3V
32k Point FFT, f = 15.11MHz,
IN
SENSE
–1dB, PGA = 0, RAND “On”,
Dither “OFF”
OV
DD
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
V
0.5V TO 3.6V
CM
0
–10
0.1µF
2.2µF
–20
OF
CLKOUT
D13
+
AIN
–30
+
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
CORRECTION
LOGIC AND
SHIFT REGISTER
CMOS
OR
LVDS
–40
ANALOG
INPUT
S/H
AMP
•
•
•
–50
–
–
–60
AIN
D0
–70
–80
OGND
–90
CLOCK/DUTY
CYCLE
CONTROL
–100
–110
–120
3.3V
V
DD
0.1µF
0.1µF
GND
0.1µF
0
20
30
40
50
60
10
220814 TA01
+
–
FREQUENCY (MHz)
ENC
ENC
PGA SHDN DITH MODE LVDS RAND
ADC CONTROL INPUTS
220814 G05
220814f
1