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LSH33JC30 PDF预览

LSH33JC30

更新时间: 2024-09-23 22:14:19
品牌 Logo 应用领域
逻辑 - LOGIC 移位寄存器
页数 文件大小 规格书
8页 221K
描述
32-bit Barrel Shifter with Registers

LSH33JC30 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ,
针数:68Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.39.00.01
风险等级:5.92其他特性:ICC SPECIFIED @ 5MHZ
边界扫描:NO最大时钟频率:33.33 MHz
外部数据总线宽度:32JESD-30 代码:S-PQCC-J68
JESD-609代码:e0长度:24.2316 mm
低功率模式:NO湿度敏感等级:3
端子数量:68最高工作温度:70 °C
最低工作温度:输出数据总线宽度:16
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:5.08 mm最大压摆率:30 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:24.2316 mm
uPs/uCs/外围集成电路类型:DSP PERIPHERAL, BARREL SHIFTERBase Number Matches:1

LSH33JC30 数据手册

 浏览型号LSH33JC30的Datasheet PDF文件第2页浏览型号LSH33JC30的Datasheet PDF文件第3页浏览型号LSH33JC30的Datasheet PDF文件第4页浏览型号LSH33JC30的Datasheet PDF文件第5页浏览型号LSH33JC30的Datasheet PDF文件第6页浏览型号LSH33JC30的Datasheet PDF文件第7页 
LSH33  
32-bit Barrel Shifter with Registers  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
SHIFT ARRAY  
The LSH33 is a 32-bit high speed  
shifter designed for use in floating  
point normalization, word pack/  
unpack, field extraction, and similar  
applications. It has 32 data inputs,  
and 16 output lines. Any shift con-  
figuration of the 32 inputs, including  
circular (barrel) shifting, left shifts  
with zero fill, and right shifts with  
sign extension are possible. In addi-  
tion, a built-in priority encoder is  
provided to aid floating point normal-  
ization.  
32-bit Input, 32-bit Output Multi-  
plexed to 16 Lines  
The 32 inputs, which can be regis-  
tered, to the LSH33 are applied to a  
32-bit shift array. The 32 outputs,  
which can also be registered, of this  
array are then multiplexed down to  
16 lines for presentation at the device  
outputs. The array may be configured  
such that any contiguous 16-bit field  
(including wraparound of the 32  
inputs) may be presented to the  
output pins under control of the shift  
code field (wrap mode). Alterna-  
tively, the wrap feature may be  
disabled, resulting in zero or sign bit  
fill, as appropriate (fill mode). The  
shift code control assignments and the  
resulting input to output mapping for  
the wrap mode are shown in Table 1.  
Full 0-31 Position Barrel Shift  
Capability  
Integral Priority Encoder for 32-bit  
Floating Point Normalization  
Sign-Magnitude or Two’s Comple-  
ment Mantissa Representation  
32-bit Linear Shifts with Sign or  
Zero Fill  
Independent Priority Encoder  
Outputs for Block Floating Point  
68-pin PLCC, J-Lead  
Input/Output registers provide  
complete pipelined operation. Both  
have independent bypass paths for  
complete flexibility. When FTI = 1,  
the input registers are bypassed.  
Likewise, when FTO= 1, the output  
registers are bypassed.  
Essentially the LSH33 is configured as  
a left shift device. That is, a shift code  
of 000002 results in no shift of the  
input field. A code of 000012 provides  
an effective left shift of 1 position, etc.  
When viewed as a right shift, the shift  
code corresponds to the two’s comple-  
ment of the shift distance, i.e., a shift  
code of 111112 (–110) results in a right  
shift of one position, etc.  
LSH33 BLOCK DIAGRAM  
SIGN  
I31-I0  
CLK  
ENI  
G
G
2:1  
2:1  
FTI  
32  
32:5  
PRIORITY  
ENCODE  
When not in the wrap mode, the  
LSH33 fills bit positions for which  
there is no corresponding input bit.  
The fill value and the positions filled  
depend on the RIGHT/LEFT (R/L)  
direction pin. This pin is a don’t care  
input when in wrap mode. For left  
shifts in fill mode, lower bits are filled  
with zero as shown in Table 2. For  
right shifts, however, the SIGN input  
is used as the fill value. Table 3  
32  
5
32-bit  
BARREL  
SHIFT  
RIGHT/LEFT  
FILL/WRAP  
ARRAY  
16  
16  
G
CLK  
G
G
ENO  
depicts the bits to be filled as a  
function of shift code for the right shift  
case. Note that the R/L input changes  
only the fill convention, and does not  
affect the definition of the shift code.  
5
2:1  
2:1  
2:1  
FTO  
5
NORM  
2:1  
16  
MS/LS  
OE  
SI/O4-SI/O0  
Y
15-Y0  
Special Arithmetic Functions  
08/16/2000–LDS.33-O  
1

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