Datasheet > LS842_SOT-23

LS842_SOT-23

更新时间： 2025-07-18 11:43:51

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MONOLITHIC DUAL N-CHANNEL JFET

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LS842_SOT-23 数据手册

LS842

MONOLITHIC DUAL

N-CHANNEL JFET

Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET

FEATURES

LOW DRIFT

LOW LEAKAGE

LOW NOISE

LOW OFFSET VOLTAGE

The LS842 is a high-performance monolithic dual

| V _GS1‐2/ T| ≤40µV/°C

I_G= 10pA TYP.

e_n= 8nV/√Hz TYP.

| V _GS1‐2|≤ 25mV

JFET featuring extremely low noise, tight offset voltage

and low drift over temperature specifications, and is

targeted for use in a wide range of precision

instrumentation applications. The LS842 features a 25-

mV offset and 40-µV/°C drift.

ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)

Maximum Temperatures

Storage Temperature

Operating Junction Temperature

The 6 Pin SOT-23 package provides ease of

manufacturing, and a lower cost assembly option.

‐65°C to +150°C

+150°C

Maximum Voltage and Current for Each Transistor – Note 1

(See Packaging Information).

‐V_GSS

‐V_DSO

‐I_G(f)

Gate Voltage to Drain or Source

Drain to Source Voltage

Gate Forward Current

60V

50mA

LS842 Applications:

Maximum Power Dissipation

Device Dissipation @ Free Air – Total

400mW @ +125°C

Wideband Differential Amps

High-Speed,Temp-Compensated Single-

Ended Input Amps

High-Speed Comparators

Impedance Converters and vibrations

detectors.

MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED

SYMBOL

CHARACTERISTICS VALUE UNITS CONDITIONS

| V _GS1‐2/ T| max.

DRIFT VS.

µV/°C

V_DG=20V, I_D=200µA

T_A=‐55°C to +125°C

V_DG=20V, I_D=200µA

TEMPERATURE

| V _GS1‐2| max.

OFFSET VOLTAGE

ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)

SYMBOL

BV_GSS

BV_GGO

CHARACTERISTICS

Breakdown Voltage

Gate‐To‐Gate Breakdown

TRANSCONDUCTANCE

Full Conduction

MIN.

TYP.

‐‐

MAX.

‐‐

UNITS

CONDITIONS

V_DS= 0

I _G= 1nA

I_D=1nA

I_D= 0

I_S= 0

Y_fSS

Y_fS

|Y_FS1‐2/ Y _FS|

1000

500

‐‐

0.6

4000

1000

µmho

V_DG= 20V

V_GS= 0V f = 1kHz

I_D= 200µA

Typical Operation

Mismatch

DRAIN CURRENT

Full Conduction

I_DSS

0.5

V_DG= 20V

V_GS= 0V

Click To Buy

|I_DSS1‐2/ I_DSS

Mismatch at Full Conduction

‐‐

GATE VOLTAGE

V_GS(off) or V_p

V_GS(on)

Pinchoff voltage

Operating Range

GATE CURRENT

Operating

High Temperature

Reduced V_DG

0.5

‐‐

4.5

V_DS= 20V

V_DS=20V

I_D= 1nA

I_D=200µA

‐I_Gmax.

‐I_GSSmax.

‐‐

V_DG= 20V I_D= 200µA

T_A= +125°C

V_DG= 10V I_D= 200µA

V_DG= 20V , V_DS=0

At Full Conduction

OUTPUT CONDUCTANCE

Full Conduction

‐‐

100

Y_OSS

Y_OS

‐‐

0.1

0.01

0.1

µmho

V_DG= 20V

V_GS= 0V

I_D= 200µA

Operating

Differential

|Y_OS1‐2

COMMON MODE REJECTION

CMR

‐20 log | V _GS1‐2/ V _DS

NOISE

‐‐

100

‐‐

∆V_DS= 10 to 20V

∆V_DS= 5 to 10V

V_DS= 20V V_GS= 0V

f= 100Hz

I_D=200µA

R_G= 10MΩ

NBW= 6Hz

e_n

Figure

Voltage

‐‐

0.5

nV/√Hz

V_DS=20V I_D=200µA f=1KHz NBW=1Hz

V_DS=20V I_D=200µA f=10Hz NBW=1Hz

CAPACITANCE

Input

Reverse Transfer

Drain‐to‐Drain

C_ISS

C_RSS

C_DD

‐‐

1.2

0.1

V_DS= 20V, I_D=200µA

‐‐

Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired

Available Packages:

LS842 / LS842 in SOT-23

LS842 / LS842 available as bare die

Please contact Micross for full package and die dimensions

Tel: +44 1603 788967

Email: chipcomponents@micross.com

Web: http://www.micross.com/distribution

Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or

other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.

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