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LS3250B_P-DIP

更新时间： 2024-02-08 11:45:03
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Linear Systems Log Conformance Monolithic Dual NPN

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LS3250B_P-DIP 数据手册

  
LS3250B  
MONOLITHIC DUAL  
NPN TRANSISTOR  
Linear Systems Log Conformance Monolithic Dual NPN  
FEATURES  
TIGHT MATCHING  
The LS3250B is a monolithic pair of NPN transistors  
mounted in a single P-DIP package. The monolithic  
dual chip design reduces parasitics and is ideal for use  
in tracking applications.  
≤ 5mV  
≤ 5µV / °C  
THERMAL TRACKING  
ABSOLUTE MAXIMUM RATINGS 1  
@ 25°C (unless otherwise noted)  
The 8 Pin P-DIP provides ease of manufacturing, and  
the symmetrical pinout prevents improper orientation.  
Maximum Temperatures  
Storage Temperature  
‐65°C to +150°C  
‐55°C to +150°C  
(See Packaging Information).  
Operating Junction Temperature  
Maximum Power Dissipation  
Continuous Power Dissipation  
Maximum Currents  
Collector Current  
Maximum Voltages  
LS3250B Features:  
TBD  
50mA  
80V  
ƒ
ƒ
Tight matching  
Low Output Capacitance  
Collector to Collector Voltage  
MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated)  
SYMBOL  
|VBE1 – VBE2  
CHARACTERISTIC  
Base Emitter Voltage Differential  
MIN  
‐‐  
TYP  
‐‐  
MAX  
5
UNITS  
mV  
CONDITIONS  
|
IC = 10mA, VCE = 5V  
∆|(VBE1 – VBE2)| / ∆T  
Base Emitter Voltage Differential  
Change with Temperature  
Base Current Differential  
‐‐  
‐
5
µV/°C  
IC = 10µA, VCE = 5V  
TA = ‐40°C to +85°C  
IC = 10µA, VCE = 5V  
|IB1 – IB2  
|
‐‐  
‐‐  
‐‐  
‐‐  
10  
nA  
|∆ (IB1 – IB2)|/ ∆T  
Base Current Differential  
Change with Temperature  
DC Current Gain Differential  
0.5  
nA/°C  
IC = 10µA, VCE = 5V  
TA = ‐40°C to +85°C  
IC = 10µA, VCE = 5V  
hFE1 /hFE2  
‐‐  
‐‐  
10  
%
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)  
SYMBOL  
BVCBO  
CHARACTERISTICS  
MIN.  
40  
TYP.  
‐‐  
MAX.  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
0.25  
0.2  
0.2  
2
1
600  
3
UNITS  
V
V
V
V
CONDITIONS  
IC = 10mA, IE = 0  
IC = 10µA, IB = 0  
IE = 10µA, IC = 0  
Collector to Base Voltage  
Click To Buy  
BVCEO  
Collector to Emitter Voltage  
Emitter‐Base Breakdown Voltage  
Collector to Collector Voltage  
40  
6.2  
80  
100  
80  
80  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
‐‐  
2
BVEBO  
BVCCO  
IC = 10µA, IE = 0  
IC = 10µA, VCE = 5V  
IC = 100µA, VCE = 5V  
IC = 1mA, VCE = 5V  
IC = 100mA, IB = 10mA  
IC = 0A, VCB = 3V  
hFE  
DC Current Gain  
VCE(SAT)  
IEBO  
ICBO  
COBO  
IC1C2  
fT  
Collector Saturation Voltage  
Emitter Cutoff Current  
Collector Cutoff Current  
V
nA  
nA  
pF  
nA  
MHz  
dB  
IE = 0A, VCB = 20V  
IE = 0A, VCB = 10V  
Output Capacitance  
Collector to Collector Leakage Current  
Current Gain Bandwidth Product  
Narrow Band Noise Figure  
VCC = ±80V  
‐‐  
‐‐  
IC = 1mA, VCE = 5V  
IC = 100µA, VCE = 5V, BW=200Hz, RB= 10Ω,  
f = 1KHz  
NF  
Notes:  
1. Absolute Maximum ratings are limiting values above which serviceability may be impaired  
2. The reverse base‐to‐emitter voltage must never exceed 6.2 volts; the reverse base‐to‐emitter current must never exceed 10µA.  
P-DIP (Top View)  
Available Packages:  
LS3250B in P-DIP  
LS3250B available as bare die  
Please contact Micross for full package and die dimensions:  
Email: chipcomponents@micross.com  
Web: www.micross.com/distribution.aspx  
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or  
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.  
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