Datasheet > LS1240

LS1240

更新时间： 2024-02-02 09:46:12

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线驱动器光电二极管
页数	文件大小	规格书
4页	43K
描述
Octal 3-STATE Bus Driver

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

LS1240 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP, DIP8,.3
针数：	8	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.56
Is Samacsys：	N	JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e3	长度：	9.652 mm
功能数量：	1	端子数量：	8
最高工作温度：	70 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	26 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	子类别：	Telephone Circuits
标称供电电压：	26 V	表面贴装：	NO
电信集成电路类型：	TELEPHONE RINGER CIRCUIT	温度等级：	OTHER
端子面层：	Matte Tin (Sn)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

LS1240 数据手册

September 1986

Revised February 2000

DM74ALS1240A

Octal 3-STATE Bus Driver

General Description

Features

These octal 3-STATE bus drivers are designed to provide

the designer with flexibility in implementing a bus interface

with memory, microprocessor, or communication systems,

and are low power dissipation versions of the

DM74ALS240A and DM74ALS241A. The output 3-STATE

gating control is organized into two separate groups of four

buffers. The DM74ALS1240A control inputs symmetrically

enable the respective outputs when set logic LOW. The 3-

STATE circuitry contains a feature that maintains the buffer

outputs in 3-STATE (high impedance state) during power

supply ramp-up or ramp-down. This eliminates bus glitch-

ing problems that arise during power-up and power-down.

■ Advanced oxide-isolated, ion-implanted Schottky TTL

process

■ Switching response specified into 500Ω and 50 pF load

■ Switching response specifications guaranteed over full

temperature and V_CCsupply range

■ PNP input design reduces input loading

■ Low power dissipation version

■ Low level drive current: 74ALS = 16 mA

Ordering Code:

Order Number

Package Number

Package Description

DM74ALS1240AWM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Logic Diagram

Function Table

Input

Output

H = HIGH Level Logic State

L = LOW Level Logic State

X = Don't Care (Either LOW or HIGH Level Logic State)

Z = High Impedance (OFF) State

DS006261

www.fairchildsemi.com

12 3 4

下载PDF

与LS1240相关器件

型号	品牌	描述	获取价格	数据表
LS1240A	STMICROELECTRONICS	ELECTRONIC TWO - TONE RINGER	获取价格
LS1240A	Wing Shing	Electronic Two-Tone Ringer	获取价格
LS1240A	UTC	ELECTRONIC TONE RINGER WITH BUILT-IN BRIDGE RECTIFIER	获取价格
LS1240A(8SOP)	UTC	Telephone Circuit, PDSO8	获取价格
LS1240A_15	UTC	ELECTRONIC TONE RINGER WITH BUILT-IN BRIDGE RECTIFIER	获取价格
LS1240A-D08-T	UTC	ELECTRONIC TONE RINGER WITH BUILT-IN BRIDGE RECTIFIER	获取价格