Datasheet > LS1026AXN8T1A

LS1026AXN8T1A

更新时间： 2024-09-24 15:18:11

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
194页	2019K
描述
Layerscape 64-bit Arm Cortex-A72, Dual-core, 1.8GHz, -40 to 105C, Security disabled

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LS1026AXN8T1A 数据手册

Document Number LS1046A

Rev. 4, 06/2020

NXP Semiconductors

Data Sheet: Technical Data

LS1046A

QorIQ LS1046A, LS1026A

Data Sheet

Features

• Additional peripheral interfaces

– One Quad Serial Peripheral Interface (QSPI)

controller

• LS1046A has four cores and LS1026A has two cores

• Four 32-bit/64-bit Arm® Cortex®-v8 A72 CPUs

– Arranged as a single cluster of four cores sharing a

single 2 MB L2 cache

– One Serial Peripheral Interface (SPI) controller

– Integrated flash controller (IFC) supporting NAND

and NOR flash

– Up to 1.8 GHz operation

– Single-threaded cores with 32 KB L1 data cache and

48 KB L1 instruction cache

– Three high-speed USB 3.0 controllers with

integrated PHY

– One Enhanced Secure Digital Host Controller

supporting SD 3.0, eMMC 4.4, and eMMC 4.5

– Four I2C controllers

– Two 16550-compliant DUARTs and six low-power

UARTs (LPUARTs)

– General purpose IO (GPIO), eight Flextimers

– One Queue Direct Memory Access Controller

(qDMA)

• Hierarchical interconnect fabric

– Up to 700 MHz operation

• One 32-bit/64-bit DDR4 SDRAM memory controller

with ECC and interleaving support

– Up to 2.1 GT/s

• Data Path Acceleration Architecture (DPAA)

incorporating acceleration for the following functions:

– Packet parsing, classification, and distribution

(FMan)

– One Enhanced Direct Memory Access Controller

(eDMA)

– Global programmable interrupt controller (GIC)

– Thermal monitoring unit (TMU)

– Queue management for scheduling, packet

sequencing, and congestion management (QMan)

– Hardware buffer management for buffer allocation

and de-allocation (BMan)

• 780 FC-PBGA package, 23 mm x 23 mm

– Cryptography acceleration (SEC)

– IEEE 1588™ support

• Two RGMII interfaces

• Eight SerDes lanes for high-speed peripheral interfaces

– Three PCI Express 3.0 controllers

– One Serial ATA (SATA 6 Gbit/s) controller

– Up to two XFI (10 GbE) interfaces

– Up to five SGMII interfaces supporting 1000 Mbps

– Up to three SGMII interfaces supporting 2500 Mbps

– Up to one QSGMII interface

– Supports 10GBase-KR

– Supports 1000Base-KX

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

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