Datasheet > LPR200JC15

LPR200JC15

更新时间： 2024-09-23 23:48:03

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
8页	234K
描述
Pipeline Register

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LPR200JC15 数据手册

LPR200

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

LPR200

16-bit Multilevel Pipeline Register

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The LPR200 is a programmable

multilevel pipeline register. This

device is pin-for-pin compatible with

the IDT73200.

The Select lines, S2-0, control an 8-to-1

multiplexer which routes the contents

of any of the registers to the Y output

pins. The independence of the I and S

controls allow simultaneous write and

read operations on different registers.

❑ Eight 16-bit High-Speed Pipeline

Registers

❑ Programmable Multilevel Register

Configurations

❑ Access time of 15 ns

❑ Hold, Shift, and Load Instructions

❑ Replaces IDT73200

The LPR200 contains eight 16-bit

high-speed pipeline registers which

can be configured as eight independent,

1-level pipelines; four independent,

2-level pipelines; two independent,

4-level pipelines; or as one 8-level

pipeline.

❑ 52-pin PLCC, J-Lead

The Instruction pins, I3-0, control the

loading of the registers. The registers

can be configured as an eight-stage

delay line with data loaded into A

and shifted sequentially through B, C,

D, E, F, G and H as shown in Table 1.

The Instruction pins may also be set

to prevent any register from changing.

LPR200 BLOCK DIAGRAM

A REG

B REG

C REG

D15-0

D REG

E REG

F REG

G REG

H REG

Y15-0

SEL2-0

3-0

CLK

CEN

Pipeline Registers

08/16/2000–LDS.P200-C

12 3 4 5 6 7 8

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