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LPC804M101JDH24FP PDF预览

LPC804M101JDH24FP

更新时间: 2024-11-26 20:44:31
品牌 Logo 应用领域
恩智浦 - NXP 时钟微控制器外围集成电路
页数 文件大小 规格书
87页 2733K
描述
RISC Microcontroller

LPC804M101JDH24FP 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
风险等级:1.66Samacsys Description:ARM Microcontrollers - MCU Cortex-M0 32KB 4KB 2 I2c, SPI, 21 GPIO
具有ADC:YES地址总线宽度:
位大小:8最大时钟频率:15 MHz
DMA 通道:YES外部数据总线宽度:
长度:7.8 mm湿度敏感等级:1
I/O 线路数量:21端子数量:24
PWM 通道:YES封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260速度:15 MHz
最大供电电压:3.6 V最小供电电压:1.71 V
标称供电电压:3.3 V表面贴装:YES
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

LPC804M101JDH24FP 数据手册

 浏览型号LPC804M101JDH24FP的Datasheet PDF文件第2页浏览型号LPC804M101JDH24FP的Datasheet PDF文件第3页浏览型号LPC804M101JDH24FP的Datasheet PDF文件第4页浏览型号LPC804M101JDH24FP的Datasheet PDF文件第5页浏览型号LPC804M101JDH24FP的Datasheet PDF文件第6页浏览型号LPC804M101JDH24FP的Datasheet PDF文件第7页 
LPC804  
32-bit Arm® Cortex®-M0+ microcontroller; up to 32 KB flash  
and 4 KB SRAM; 12-bit ADC; Comparator; 10-bit DAC;  
Capacitive Touch Interface; Programmable Logic Unit  
Rev. 1.4 — 12 July 2018  
Product data sheet  
1. General description  
The LPC804 are an ArmCortex-M0+ based, low-cost 32-bit MCU family operating at CPU  
frequencies of up to 15 MHz. The LPC804 supports 32 KB of flash memory and 4 KB of  
SRAM.  
The peripheral complement of the LPC804 includes a CRC engine, two I2C-bus  
interfaces, up to two USARTs, one SPI interface, Capacitive Touch Interface (Cap Touch),  
one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one  
12-bit ADC, one 10-bit DAC, one analog comparator, function-configurable I/O ports  
through a switch matrix, an input pattern match engine, Programmable Logic Unit (PLU),  
and up to 30 general-purpose I/O pins.  
For additional documentation related to the LPC804 parts, see Section 19.  
2. Features and benefits  
System:  
Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 15 MHz  
with single-cycle multiplier and fast single-cycle I/O port.  
Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  
System tick timer.  
AHB multilayer matrix.  
Serial Wire Debug (SWD) with four break points and two watch points. JTAG  
boundary scan (BSDL) supported.  
Memory:  
Up to 32 KB on-chip EEPROM based flash programming memory.  
Code Read Protection (CRP).  
4 KB SRAM.  
Dual I/O power (LPC804M111JDH24):  
Independent supplies on each package side permitting level-shifting signals from  
one off-chip voltage domain to another and/or interfacing directly to off-chip  
peripherals operating at different supply levels.  
The switch matrix provides level shifter functionality to allow up to two selected  
signals to be routed from user-selected pins in one voltage domain to selected pins  
in the alternate domain. This feature can also be used on a single supply device if  
voltage level shifting is not required.  
ROM API support:  
Boot loader.  
 
 

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