Datasheet > LPC5526JEV98

LPC5526JEV98

更新时间： 2024-03-03 10:08:24

品牌	Logo	应用领域
恩智浦 - NXP		PC 微控制器
页数	文件大小	规格书
140页	3623K
描述
LPC552x/S2x: Mainstream Arm^® Cortex^®-M33-based Microcontroller Famil...

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LPC5526JEV98 数据手册

LPC55S2x/LPC552x

32-bit Arm Cortex^®-M33, CASPER, 256 KB SRAM; 512 KB

flash, USB HS, Flexcomm Interface, SDIO, 32-bit counter/

timers, SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,

Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG

Rev. 2.2 — 8 December 2022

Product data sheet

1. General description

The LPC55S2x/LPC552x is an ARM Cortex-M33 based microcontroller for embedded

applications. These devices include a CASPER Crypto/FFT engine, up to 256 KB of

on-chip SRAM, up to 512 KB on-chip flash, PRINCE module for on-the-fly flash

encryption/decryption, high-speed and full-speed USB host and device interface with

crystal-less operation for full-speed, SD/MMC/SDIO interface, five general-purpose

timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a

Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals

(which can be configured as a USART, SPI, high speed SPI, I²C, or I²S interface),

Programmable Logic Unit (PLU), one 16-bit 1.0 Msamples/sec ADC capable of

simultaneous conversions, comparator, and temperature sensor.

To support security requirements, the LPC55S2x also offers support for secure boot,

HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug authentication, and TBSA

compliance.

2. Features and benefits

 ARM Cortex-M33 core (r0p3):

 Running at a frequency of up to 150 MHz.

 Memory Protection Unit (MPU).

 ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-maskable Interrupt (NMI) input with a selection of sources.

 Serial Wire Debug with eight breakpoints and four watch points. Includes Serial

Wire Output for enhanced debug capabilities.

 System tick timer.

 The configuration of this instance includes MPU, FPU, DSP, and ETM.

 CASPER Crypto co-processor is provided to enable hardware acceleration for various

functions required for certain asymmetric cryptographic algorithms, such as, Elliptic

Curve Cryptography (ECC).

 On-chip memory:

 Up to 512 KB on-chip flash program memory with flash accelerator and 512 byte

page erase and write.

 Up to 256 KB total SRAM consisting of 32 KB SRAM on Code Bus, 208 KB SRAM

on System Bus (192 KB is contiguous), and additional 16 KB USB SRAM on

System Bus which can be used by the USB interface or for general purpose use.

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