Datasheet > LPC11E14FHN33

LPC11E14FHN33

更新时间： 2024-01-18 18:36:30

品牌	Logo	应用领域
恩智浦 - NXP		微控制器
页数	文件大小	规格书
66页	1397K
描述
Scalable Entry Level 32-bit Microcontroller (MCU) based on ARM Cortex-M0+/M0 Cores

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LPC11E14FHN33 数据手册

LPC11E3x

32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up

to 12 kB SRAM and 4 kB EEPROM; USART

Rev. 2 — 21 November 2013

Product data sheet

1. General description

The LPC11E3x are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit

microcontroller applications, offering performance, low power, simple instruction set and

memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC11E3x operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC11E3x includes up to 128 kB of flash memory, up to

12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I²C-bus interface,

one RS-485/EIA-485 USART with support for synchronous mode and smart card

interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up

to 54 general purpose I/O pins.

The I/O Handler is a software library-supported hardware engine that can be used to add

performance, connectivity and flexibility to system designs. It is available on the

LPC11E37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,

I²C, and I²S with no or very low additional CPU load and can off-load the CPU by

performing processing-intensive functions like DMA transfers in hardware. Software

libraries for multiple I/O Handler applications are available on http://www.LPCware.com.

2. Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Non Maskable Interrupt (NMI) input selectable from several input sources.

 System tick timer.

 Memory:

 Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase

(256 byte) access.

 4 kB on-chip EEPROM data memory; byte erasable and byte programmable;

on-chip API support.

 12 kB SRAM data memory.

 16 kB boot ROM.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 ROM-based 32-bit integer division routines.

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