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LP5551SQ PDF预览

LP5551SQ

更新时间: 2024-11-21 03:51:59
品牌 Logo 应用领域
美国国家半导体 - NSC 模拟IC信号电路
页数 文件大小 规格书
32页 3304K
描述
PowerWise⑩ Technology Compliant Energy Management Unit

LP5551SQ 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:LLP-36Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.81Is Samacsys:N
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:S-XQCC-N36
JESD-609代码:e0长度:6 mm
湿度敏感等级:3功能数量:1
端子数量:36最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC36,.25SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:Power Management Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.6 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:6 mm
Base Number Matches:1

LP5551SQ 数据手册

 浏览型号LP5551SQ的Datasheet PDF文件第2页浏览型号LP5551SQ的Datasheet PDF文件第3页浏览型号LP5551SQ的Datasheet PDF文件第4页浏览型号LP5551SQ的Datasheet PDF文件第5页浏览型号LP5551SQ的Datasheet PDF文件第6页浏览型号LP5551SQ的Datasheet PDF文件第7页 
December 2006  
LP5551  
PowerWise™ Technology Compliant Energy Management  
Unit  
General Description  
Features  
The LP5551 is a PWI 1.0 compliant Energy Management  
System for reducing power consumption of stand-alone mo-  
bile phone processors such as base-band or applications  
processors.  
2 300 mA buck regulators operate 180 degrees out of  
phase for reduced EMI  
1 MHz PWM switching frequency  
4 programmable LDOs ideal for I/O (two of these), PLL,  
and memory retention supply generation.  
Supports high-efficiency PowerWise Technology  
Adaptive Voltage Scaling  
PWI open standard interface for system power  
management  
Digitally controlled intelligent voltage scaling  
The LP5551 contains two advanced, digitally controlled  
switching regulators for supplying variable voltage to proces-  
sor core and memory. Two regulators provide P- and N- well  
biasing for threshold scaling applications. The device also in-  
tegrates 4 programmable LDO-regulators for powering I/O,  
PLLs and maintaining memory retention in shutdown-mode.  
The device is controlled via the PWI open-standard interface.  
The LP5551 operates cooperatively with PowerWise™ tech-  
nology compatible processors to optimize supply voltages  
adaptively over process and temperature variations or dy-  
namically using frequency/voltage pre-characterized look-up  
tables and provides P- and N-well biasing for threshold scal-  
ing.  
Auto or PWI controlled PFM mode transition  
Internal soft start/startup sequencing.  
Adjustable P- and N- well bias supply for threshold scaling  
Power OK output.  
Applications  
Dual core processors  
GSM/GPRS/EDGE & UMTS cellular handsets  
Hand-held radios  
PDAs  
Battery powered devices  
Portable instruments  
System Diagram  
20172163  
FIGURE 1. System Diagram  
© 2007 National Semiconductor Corporation  
201721  
www.national.com  

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