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LMX2492-Q1RTW

更新时间: 2024-09-24 01:15:03
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德州仪器 - TI /
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描述
LMX2492/LMX2492-Q1 14 GHz Low Noise Fractional N PLL with Ramp/Chirp Generation

LMX2492-Q1RTW 数据手册

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LMX2492, LMX2492-Q1  
SNAS624B MARCH 2014REVISED MAY 2015  
LMX2492/LMX2492-Q1 14 GHz Low Noise Fractional N PLL with Ramp/Chirp Generation  
1 Features  
3 Description  
The LMX2492/92-Q1 is  
a low noise 14 GHz  
1
-227 dBc/Hz Normalized PLL Noise  
500 MHz - 14 GHz Wideband PLL  
3.15 - 5.25 V Charge Pump PLL Supply  
Versatile Ramp / Chirp Generation  
200 MHz Max Phase Detector Frequency  
FSK / PSK Modulation Pin  
wideband delta-sigma fractional N PLL with ramp and  
chirp generation. It consists of a phase frequency  
detector, programmable charge pump, and high  
frequency input for the external VCO. The  
LMX2492/92-Q1 supports a broad and flexible class  
of ramping capabilities, including FSK, PSK, and  
configurable piecewise linear FM modulation profiles  
of up to 8 segments. It supports fine PLL resolution  
and fast ramp with up to a 200 MHz phase detector  
rate. The LMX2492/92-Q1 allows any of its registers  
to be read back. The LMX2492/92-Q1 can operate  
with a single 3.3 V supply. Moreover, supporting up to  
5.25 V charge pump can eliminate the need of  
external amplifier, leading to a simpler solution with  
improved phase noise performance.  
Digital Lock Detect  
Single 3.3 V Supply Capability  
Automotive 125°C Q100 Grade 1 Qualification  
Non-Automotive (LMX2492) Option  
2
Applications  
Automotive FMCW Radar  
Military Radar  
Device Information  
Microwave Backhaul  
PART NUMBER  
LMX2492-Q1RTW WQFN (24)  
LMX2492RTW WQFN (24)  
PACKAGE  
BODY SIZE (NOM)  
4.00 mm x 4.00 mm  
4.00 mm x 4.00 mm  
Test and Measurement  
Satellite Communications  
Wireless Infrastructure  
(1) For all available packages, see the orderable addendum at  
the end of the datasheet.  
Sampling Clock for High Speed ADC/DAC  
4 Simplified Schematic  
OSCin  
2X  
R Divider  
(16 bit)  
CPout  
Vcp  
Phase  
Comp  
Charge  
Pump  
51 :  
GND/OSCin*  
C2_LF  
R2_LF  
51 :  
C1_LF  
GND (x3)  
18 :  
18 :  
Vcc (x5)  
Fin  
CE  
CLK  
DATA  
MICROWIRE  
Interface  
36 :  
18 :  
To Circuit  
N Divider  
(18 bit)  
LE  
Fin*  
68 :  
TRIG1  
TRIG2  
51 :  
6'  
Modulation  
Generator  
Compensation  
(24 bit)  
MUX  
MOD  
MUXout  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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