Datasheet > LMX2471SLEX

LMX2471SLEX

更新时间： 2024-11-21 20:10:27

品牌	Logo	应用领域
美国国家半导体 - NSC		信息通信管理
页数	文件大小	规格书
36页	446K
描述
IC PLL FREQUENCY SYNTHESIZER, 3600 MHz, QCC24, 3.5 X 4.5 MM, 0.60 MM HEIGHT, TCSP-24, PLL or Frequency Synthesis Circuit

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LMX2471SLEX 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	VQCCN, LCC24,.17X.14,20	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.72
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	R-XQCC-N24
JESD-609代码：	e0	长度：	4.5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	VQCCN	封装等效代码：	LCC24,.17X.14,20
封装形状：	RECTANGULAR	封装形式：	CHIP CARRIER, VERY THIN PROFILE
峰值回流温度（摄氏度）：	235	电源：	2.5 V
认证状态：	Not Qualified	座面最大高度：	0.6 mm
子类别：	PLL or Frequency Synthesis Circuits	最大供电电压 (Vsup)：	2.75 V
最小供电电压 (Vsup)：	2.25 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.5 mm	Base Number Matches：	1

LMX2471SLEX 数据手册

November 2003

LMX2471

3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz

Integer-N PLL

General Description

Features

n Low in-band phase noise and low fractional spurs

n 12 bit or 22 bit selectable fractional modulus

n Up to 4th order programmable delta-sigma modulator

n Enhanced Anti-Cycle Slip Fastlock Circuitry

Fastlock

The LMX2471 is a low power, high performance delta-sigma

fractional-N PLL with an auxiliary integer-N PLL. The device

is fabricated using National Semiconductor’s advanced BiC-

MOS process.

With delta-sigma architecture, fractional spur compensation

is achieved with noise shaping capability of the delta-sigma

modulator and the inherent low pass filtering of the PLL loop

filter. Fractional spurs at lower frequencies are pushed to

higher frequencies outside the loop bandwidth. Unlike ana-

log compensation, the digital feedback techniques used in

the LMX2471 are highly resistant to changes in temperature

and variations in wafer processing. With delta-sigma archi-

tecture, the ability to push close in spur and phase noise

energy to higher frequencies is a direct function of the modu-

lator order. The higher the order, the more this energy can be

spread to higher frequencies. The LMX2471 has a program-

mable modulator up to order four, which allows the designer

to select the optimum modulator order to fit the phase noise,

spur, and lock time requirements of the system.

Cycle slip reduction

Integrated timeout counters

n Digital lock detect output

n Prescalers allow wide range of N values

RF PLL: 16/17/20/21

IF PLL: 8/9 or 16/17

n Crystal Reference Frequency up to 110 MHz

n On-chip crystal reference frequency doubler.

n Phase Comparison Frequency up to 50 MHz

n Hardware and software power-down control

n Ultra low consumption: I_CC= 5.6 mA (typical)

Applications

Programming is fast and simple. Serial data is transferred

into the LMX2471 via a three line MICROWIRE interface

(Data, Clock, Load Enable). Nominal supply voltage is 2.5 V.

The LMX2471 features a typical current consumption of 5.6

mA at 2.5 V. The LMX2471 is available in a 24 lead 3.5 X 4.5

X 0.6 mm package.

n Cellular Phones and Base Stations

n Applications requiring fine frequency resolution

n Satellite and Cable TV Tuners

n WLAN Standards

Functional Block Diagram

20072101

DS200721

www.national.com

12 3 4 5 6 7...36

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与LMX2471SLEX相关器件

型号	品牌	获取价格	描述	数据表
LMX2471SLEX/NOPB	NSC	获取价格	IC,PHASE-LOCKED LOOP,BICMOS,LLCC,24PIN,PLASTIC
LMX2485	NSC	获取价格	50 MHz - 3.0 GHz High Performance Delta-Sigma
LMX2485	TI	获取价格	用于射频个人通信的 500MHz 至 3GHz Δ-Σ 低功耗双路 PLL
LMX2485_0610	NSC	获取价格	50 MHz - 3.0 GHz High Performance Delta-Sigma
LMX2485_08	NSC	获取价格	50 MHz - 3.0 GHz High Performance Delta-Sigma
LMX2485E	NSC	获取价格	50 MHz - 3.0 GHz High Performance Delta-Sigma
LMX2485E	TI	获取价格	用于射频个人通信的 50MHz 至 3GHz Δ-Σ 低功耗双路 PLL
LMX2485ESQ	NSC	获取价格	50 MHz - 3.0 GHz High Performance Delta-Sigma
LMX2485ESQ/NOPB	NSC	获取价格	IC PLL FREQUENCY SYNTHESIZER, 3000 MHz, PQCC24, 4 X 4 MM, 0.8 MM, PLASTIC, LLP-24, PLL or
LMX2485ESQ/NOPB	TI	获取价格	用于射频个人通信的 50MHz 至 3GHz Δ-Σ 低功耗双路 PLL \| RTW \|

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