Datasheet > LMUN5116T1G

LMUN5116T1G

更新时间： 2024-01-19 12:08:25

品牌	Logo	应用领域
乐山 - LRC		/
页数	文件大小	规格书
12页	174K
描述
Bias Resistor Transistor

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LMUN5116T1G 数据手册

LESHAN RADIO COMPANY, LTD.

Bias Resistor Transistor

PNP Silicon Surface Mount Transistor

LMUN5111T1G

SERIES

with Monolithic Bias Resistor Network

PNP SILICON

BIAS RESISTOR

TRANSISTORS

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The BRT (Bias Resistor

Transistor) contains a single transistor with a monolithic bias network

consisting of two resistors; a series base resistor and a base–emitter

resistor. The BRT eliminates these individual components by integrating

them into a single device. The use of a BRT can reduce both system cost

and board space. The device is housed in the SC–70/SOT–323 package

which is designed for low power surface mount applications.

CASE 419, STYLE 3

SOT–323 (SC–70)

PIN 2

COLLECTOR

(OUTPUT)

R₁

R₂

PIN 1

• Simplifies Circuit Design

BASE

(INPUT)

PIN 3

EMITTER

• Reduces Board Space

(GROUND)

• Reduces Component Count

• The SC–70/SOT–323 package can be soldered using wave or reflow.

The modified gull–winged leads absorb thermal stress during soldering

eliminating the possibility of damage to the die.

MARKINGDIAGRAM

• We declare that the material of product compliance with RoHS requirements.

Ordering Information

Device

Package

Shipping

6 X

=Specific Device Code

=(See Marking Table)

=Date Code

LMUN51XXT1G

SOT323

3000/Tape&Reel

LMUN51XXT3G

SOT323

10000/Tape&Reel

MAXIMUM RATINGS (T_A= 25°C unless otherwise noted)

Rating

Symbol

V_CBO

Value

Unit

Vdc

Collector-Base Voltage

Collector-Emitter Voltage

Collector Current

V_CEO

Vdc

100

mAdc

THERMAL CHARACTERISTICS

Characteristic

Symbol

Max

Unit

Total Device Dissipation

T_A= 25°C

202 (Note 1)

310 (Note 2)

1.6 (Note 1)

2.5 (Note 2)

618 (Note 1)

403 (Note 2)

280 (Note 1)

332 (Note 2)

–55 to +150

Derate above 25°C

°C/W

°C

Thermal Resistance –

Junction-to-Ambient

Thermal Resistance –

Junction-to-Lead

R_θJA

R_θJL

Junction and Storage

Temperature Range

T_J,T_stg

1. FR–4 @ Minimum Pad

2. FR–4 @ 1.0 x 1.0 inch Pad

1/12

12 3 4 5 6 7...12

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