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LMU8UJC35 PDF预览

LMU8UJC35

更新时间: 2024-01-18 13:19:07
品牌 Logo 应用领域
逻辑 - LOGIC /
页数 文件大小 规格书
7页 178K
描述
8 x 8-bit Parallel Multiplier

LMU8UJC35 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
零件包装代码:LCC包装说明:QCCJ, LDCC44,.7SQ
针数:44Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.39.00.01
风险等级:5.88其他特性:2 X 8 BIT DATA INPUT BUS; ICC SPECIFIED AT 5MHZ
边界扫描:NO最大时钟频率:28.57 MHz
外部数据总线宽度:8JESD-30 代码:S-PQCC-J44
JESD-609代码:e0长度:16.5862 mm
低功率模式:NO湿度敏感等级:3
端子数量:44最高工作温度:70 °C
最低工作温度:输出数据总线宽度:16
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:DSP Peripherals最大压摆率:24 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:16.5862 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, MULTIPLIER

LMU8UJC35 数据手册

 浏览型号LMU8UJC35的Datasheet PDF文件第2页浏览型号LMU8UJC35的Datasheet PDF文件第3页浏览型号LMU8UJC35的Datasheet PDF文件第4页浏览型号LMU8UJC35的Datasheet PDF文件第5页浏览型号LMU8UJC35的Datasheet PDF文件第6页浏览型号LMU8UJC35的Datasheet PDF文件第7页 
LMU08/8U  
8 x 8-bit Parallel Multiplier  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The LMU08 and LMU8U are high-  
speed, low power 8-bit parallel  
multipliers. They are pin-for-pin  
equivalents with TRW TMC208K and  
TMC28KU type multipliers. Full  
military ambient temperature range  
operation is attained by the use of  
advanced CMOS technology.  
This facilitates use of the LMU08  
product as a double precision operand  
in 8-bit systems. The LMU8U oper-  
ates on unsigned data, producing an  
unsigned magnitude result.  
20 ns Worst-Case Multiply Time  
LowPowerCMOSTechnology  
LMU08 Replaces TRW TMC208K  
LMU8UReplacesTRWTMC28KU  
Two’sComplement(LMU08),or  
Both the LMU08 and the LMU8U  
feature independently controlled  
registers for both inputs and the  
product, which along with three-state  
outputs allows easy interfacing with  
microprocessor busses. Provision is  
Unsigned Operands (LMU8U)  
Three-State Outputs  
Package Styles Available:  
Both the LMU08 and the LMU8U  
produce the 16-bit product of two  
8-bit numbers. The LMU08 accepts  
• 40-pin PDIP  
• 44-pinPLCC, J-Lead  
operands in two’s complement format, made in the LMU08 and LMU8U for  
and produces a two’s complement proper rounding of the product to  
result. The product is provided in two 8-bit precision. The round input is  
halves with the sign bit replicated as loaded at the rising edge of the logical  
the most significant bit of both halves. OR of CLK A and CLK B for the  
LMU08. The LMU8U latches RND on  
the rising edge of CLK A only. In  
either case, a ‘1’ is added in the most  
LMU08/8U BLOCK DIAGRAM  
significant position of the lower  
A
7-0  
B7-0  
product byte when RND is asserted.  
Subsequent truncation of the least  
significant product byte results in a  
correctly rounded 8-bit result.  
8
8
CLK A  
CLK B  
A REGISTER  
B REGISTER  
LMU08 Only  
RND  
16  
8
8
CLK R  
RESULT  
REGISTER  
OEM  
OEL  
8
8
R
15-8  
R7-0  
Multipliers  
08/16/2000–LDS.08/8U-R  
1

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