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LMU18JC45 PDF预览

LMU18JC45

更新时间： 2024-09-23 22:09:19
品牌 Logo 应用领域
逻辑 - LOGIC /
页数 文件大小 规格书
7页 187K
描述
16 x 16-bit Parallel Multiplier

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中文翻译

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LMU18JC45 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer零件包装代码：LCC
包装说明：QCCJ, LDCC84,1.2SQ针数：84
Reach Compliance Code：compliant风险等级：5.78
其他特性：2 X 16 BIT DATA INPUT BUS; ICC SPECIFIED AT 5MHZ边界扫描：NO
最大时钟频率：22.22 MHz外部数据总线宽度：16
JESD-30 代码：S-PQCC-J84JESD-609代码：e0
长度：29.3116 mm低功率模式：NO
湿度敏感等级：3端子数量：84
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：32封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC84,1.2SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：DSP Peripherals最大压摆率：45 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：29.3116 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, MULTIPLIERBase Number Matches：1

LMU18JC45 数据手册

 浏览型号LMU18JC45的Datasheet PDF文件第2页浏览型号LMU18JC45的Datasheet PDF文件第3页浏览型号LMU18JC45的Datasheet PDF文件第4页浏览型号LMU18JC45的Datasheet PDF文件第5页浏览型号LMU18JC45的Datasheet PDF文件第6页浏览型号LMU18JC45的Datasheet PDF文件第7页 
LMU18  
16 x 16-bit Parallel Multiplier  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The LMU18 is a high-speed, low by the ENA and ENB controls. When  
power 16-bit parallel multiplier. HIGH, these controls prevent appli-  
The LMU18 is an 84-pin device cation of the clock to the respective  
which provides simultaneous access register. The TCA and TCB controls  
❑ 35 ns Worst-Case Multiply Time  
❑ Low Power CMOS Technology  
❑ Full 32-bit Output Port —  
No Multiplexing Required  
to all outputs.  
specify the operands as two’s com-  
plement when HIGH, or unsigned  
magnitude when LOW.  
❑ Two’s Complement, Unsigned, or  
Mixed Operands  
The LMU18 produces the 32-bit  
product of two 16-bit numbers.  
❑ Three-State Outputs  
❑ 84-pin PLCC, J-Lead  
Data present at the A inputs, along RNDisloadedontherisingedgeofCLK,  
with the TCA control bit, is loaded providing either ENA or ENB are LOW.  
into the A register on the rising edge RND, when HIGH, adds ‘1’ to the  
of CLK. B data and the TCB control most significant bit position of the  
bit are similarly loaded. Loading of least significant half of the product.  
the A and B registers is controlled Subsequent truncation of the 16 least  
significant bits produces a result  
correctly rounded to 16-bit precision.  
LMU18 BLOCK DIAGRAM  
Attheoutput, theRightShiftcontrol(RS)  
selects either of two output formats. RS  
TCA  
A
15-0  
TCB  
B15-0  
LOW produces a 31-bit product with a  
copy of the sign bit inserted in the MSB  
postion of the least significant half. RS  
HIGH gives a full 32-bit product. Two  
16-bit output registers are provided to  
hold the most and least significant  
halves of the result (MSP and LSP) as  
definedbyRS. Theseregistersareloaded  
on the rising edge of CLK, subject to the  
ENRcontrol. WhenENRisHIGH, clock-  
ing of the result registers is prevented.  
16  
A REGISTER  
16  
B REGISTER  
CLK  
ENA  
ENB  
RND  
RS  
For asynchronous output these registers  
may be made transparent by setting the  
feed through control (FT) HIGH and  
ENR LOW.  
32  
FORMAT ADJUST  
The two halves of the product may be  
routed to a single 16-bit three-state  
output port (MSP) via a multiplexer.  
MSPSEL LOW causes the MSP outputs to  
be driven by the most significant half of  
the result. MSPSEL HIGH routes the  
least significant half of the result to the  
MSP pins. The MSB of the result is avail-  
able in both true and complemented  
form to aid implementation of higher  
precision multipliers.  
16  
16  
FT  
ENR  
RESULT  
REGISTER  
MSPSEL  
OEM  
OEL  
16  
16  
R
31  
R
31-16  
R15-0  
Multipliers  
08/16/2000–LDS.18-O  
1
1234567

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