Datasheet > LMU16

LMU16

更新时间： 2024-11-26 22:31:11

品牌	Logo	应用领域
逻辑 - LOGIC		/
页数	文件大小	规格书
7页	190K
描述
16 x 16-bit Parallel Multiplier

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中文翻译

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LMU16 数据手册

LMU16/216

DEVICES INCORPORATED

16 x 16-bit Parallel Multiplier

LMU16/216

16 x 16-bit Parallel Multiplier

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The LMU16 and LMU216 are high- RND is loaded on the rising edge of

❑ 20 ns Worst-Case Multiply Time

❑ Low Power CMOS Technology

❑ Replaces Fairchild MPY016/TMC216,

Cypress CY7C516, IDT 7216L, and

AMD Am29516

speed, low power 16-bit parallel

multipliers. The LMU16 and

the logical OR of CLK A and CLK B.

RND, when HIGH, adds ‘1’ to the

LMU216 are functionally identical; most significant bit position of the

they differ only in packaging.

least significant half of the product.

Subsequent truncation of the 16 least

significant bits produces a result

correctly rounded to 16-bit precision.

❑ Two’s Complement, Unsigned, or

The LMU16 and LMU216 produce

the 32-bit product of two 16-bit

numbers. Data present at the A

Mixed Operands

❑ Three-State Outputs

❑ 68-pin PLCC, J-Lead

inputs, along with the TCA control At the output, the Right Shift control

bit, is loaded into the A register on (RS) selects either of two output

the rising edge of CLK A. B data

and the TCB control bit are

similarly loaded by CLK B. The

TCA and TCB controls specify the

A and B operands as two’s

complement when HIGH, or

unsigned magnitude when LOW.

formats. RS LOW produces a 31-bit

product with a copy of the sign bit

inserted in the MSB postion of the

least significant half. RS HIGH gives a

full 32-bit product. Two 16-bit output

registers are provided to hold the

most and least significant halves of the

result (MSP and LSP) as defined by

RS. These registers are loaded on the

rising edge of CLK M and CLK L

respectively. For asynchronous

output, these registers may be made

transparent by setting the feed

LMU16/216 BLOCK DIAGRAM

15-0

TCA

15-0

TCB

through control (FT) HIGH.

A REGISTER

The two halves of the product may be

routed to a single 16-bit three-state

output port (MSP) via a multiplexer.

MSPSEL LOW causes the MSP

outputs to be driven by the most

significant half of the result. MSPSEL

HIGH routes the least significant half

of the result to the MSP outputs. In

addition, the LSP is available via the B

port through a separate three-state

buffer.

CLK A

CLK B

B REGISTER

RND

FORMAT ADJUST

The output multiplexer control

MSPSEL uses a pin which is a supply

ground in the Fairchild MPY016H/

TMC216H. When this control is LOW

(GND), the function is that of the

MPY016H/TMC216H, thus allowing

full compatibility.

CLK M

CLK L

RESULT

MSPSEL

OEM

OEL

31-16

Multipliers

08/16/2000–LDS.16/216-N

12 3 4 5 6 7

中文翻译

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与LMU16相关器件

型号	品牌	获取价格	描述	数据表
LMU16DC35	LOGIC	获取价格	Multiplier, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY-DOWN, SIDE BRAZED, HERMETIC SEALED, D
LMU16DC45	LOGIC	获取价格	Multiplier, 16-Bit, CMOS, CDIP64, SIDE BRAZED, HERMETIC SEALED, DIP-64
LMU16DC55	ETC	获取价格	Multiplier
LMU16DC65	LOGIC	获取价格	Multiplier, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY-DOWN, SIDE BRAZED, HERMETIC SEALED, D
LMU16DCR	LOGIC	获取价格	Multiplier, CMOS, CDIP64
LMU16DM-1	LOGIC	获取价格	Multiplier, CMOS, CDIP64
LMU16DM40	LOGIC	获取价格	Multiplier, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY-DOWN, SIDE BRAZED, HERMETIC SEALED, D
LMU16DM55	LOGIC	获取价格	Multiplier, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY-DOWN, SIDE BRAZED, HERMETIC SEALED, D
LMU16DM65	LOGIC	获取价格	Multiplier, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY-DOWN, SIDE BRAZED, HERMETIC SEALED, D
LMU16DM75	LOGIC	获取价格	Multiplier, 16-Bit, CMOS, CDIP64, 0.900 INCH, CAVITY-DOWN, SIDE BRAZED, HERMETIC SEALED, D

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