Datasheet > LMS12JC35

LMS12JC35

更新时间： 2024-09-23 22:11:59

品牌	Logo	应用领域
逻辑 - LOGIC		/
页数	文件大小	规格书
9页	197K
描述
12-bit Cascadable Multiplier-Summer

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LMS12JC35 数据手册

LMS12

DEVICES INCORPORATED

12-bit Cascadable Multiplier-Summer

LMS12

12-bit Cascadable Multiplier-Summer

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The LMS12 is a high-speed 12 x 12-bit ENA and ENB inputs. The registered

❑ 12 x 12-bit Multiplier with

Pipelined 26-bit Output Summer

combinatorial multiplier integrated

with a 26-bit adder in a single 84-pin

package. It is an ideal building block

for the implementation of very high-

speed FIR filters for video, RADAR,

and other similar applications. The

LMS12 implements the general form

(A•B) + C. As a result, it is also useful

in implementing polynomial approxi-

mations to transcendental functions.

input data are then applied to a

12 x 12-bit multiplier array, which

produces a 24-bit result. Both the

inputs and outputs of the multiplier

are in two’s complement format. The

multiplication result forms the input

to the 24-bit product register.

❑ Summer has 26-bit Input Port Fully

Independent from Multiplier

Inputs

❑ Cascadable to Form Video Rate FIR

Filter with 3-bit Headroom

❑ A, B, and C Input Registers Sepa-

rately Enabled for Maximum

Flexibility

SUMMER

❑ 28 MHz Data Rate for FIR Filtering

The C25-0 inputs to the LMS12 form a

26-bit two’s complement number

which is captured in the C register at

the rising edge of the clock. The C

ENC input. The summer is a 26-bit

adder which operates on the C

Applications

ARCHITECTURE

❑ High Speed, Low Power CMOS

A block diagram of the LMS12 is

shown below. Its major features are

discussed individually in the follow-

ing paragraphs.

Technology

❑ 84-pin PLCC, J-Lead

contents of the product register to

produce a 26-bit sum. This sum is

applied to the 26-bit S register.

MULTIPLIER

The A11-0 and B11-0 inputs to the

LMS12 are captured at the rising edge

of the clock in the 12-bit A and B input

registers, respectively. These registers

are independently enabled by the

OUTPUT

The FTS input is the feedthrough

control for the S register. When FTS is

asserted, the summer result is applied

directly to the S output port. When

FTS is deasserted, data from the S

effecting a one-cycle delay of the

summer result. The S output port can

be forced to a high-impedance state by

driving the OE control line high. FTS

would be asserted for conventional

FIR filter applications, however the

insertion of zero-coefficient filter taps

may be accomplished by negating

FTS. Negating FTS also allows

application of the same filter transfer

function to two interleaved datas-

treams with successive input and

output sample points occurring on

alternate clock cycles.

LMS12 BLOCK DIAGRAM

11-0

B11-0

A REGISTER

B REGISTER

ENA

CLK

ENB

PRODUCT REGISTER

SIGN

FTS

EXTENDED

25-0

S25-0

ENC

Multiplier-Summers

08/16/2000–LDS.S12-J

12 3 4 5 6 7...9

中文翻译

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与LMS12JC35相关器件

型号	品牌	获取价格	描述	数据表
LMS12JC40	LOGIC	获取价格	12-bit Cascadable Multiplier-Summer
LMS12JC50	LOGIC	获取价格	Multiplier Accumulator/Summer, 12-Bit, CMOS, PQCC84, 1.190 X 1.190 INCH, PLASTIC, MO-047-A
LMS12JC65	LOGIC	获取价格	Multiplier Accumulator/Summer, 12-Bit, CMOS, PQCC84, 1.190 X 1.190 INCH, PLASTIC, MO-047-A
LMS133ATP	VCC	获取价格	Optical Pipe
LMS133BTP	VCC	获取价格	5MM MOISTURE SEALED LITEPIPE
LMS133CTP	VCC	获取价格	Optical Pipe
LMS133GLO	VCC	获取价格	5MM MOISTURE SEALED LITEPIPE
LMS133GTP	VCC	获取价格	5MM MOISTURE SEALED LITEPIPE
LMS133RTP	VCC	获取价格	Optical Pipe
LMS133YTP	VCC	获取价格	Optical Pipe

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