Datasheet > LMK61E08-SIAR

LMK61E08-SIAR

更新时间： 2023-09-03 20:32:07

品牌	Logo	应用领域
德州仪器 - TI		可编程只读存储器电动程控只读存储器电可擦编程只读存储器振荡器
页数	文件大小	规格书
54页	925K
描述
具有内部 EEPROM 的超低抖动可编程振荡器 \| SIA \| 6 \| -40 to 85

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LMK61E08

SNAS805 –JUNE 2020

LMK61E08 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM

1 Features

3 Description

The LMK61E08 family of ultra-low jitter PLLatinum™

programmable oscillators uses fractional-N frequency

synthesizers with integrated VCOs to generate

commonly used reference clocks. The output on

LMK61E08 can be configured as LVPECL, LVDS, or

HCSL. The device features self-start-up from on-chip

EEPROM to generate a factory-programmed default

output frequency, or the device registers and

EEPROM settings are fully programmable in-system

through an I²C serial interface. The device provides

fine and coarse frequency margining control through

an I²C serial interface, making it a digitally-controlled

oscillator (DCXO).

•

Ultra-Low Noise, High Performance

–

Jitter: 90-fs RMS Typical f_OUT> 100 MHz on

LMK61E08

–

PSRR: –70 dBc, Robust Supply Noise

Immunity on LMK61E08

•

Flexible Output Format on LMK61E08

–

LVPECL up to 1 GHz

LVDS up to 900 MHz

HCSL up to 400 MHz

•

Total Frequency Tolerance of ±25 ppm

System Level Features

The PLL feedback divider can be updated to adjust

the output frequency without spikes or glitches in

steps of <1ppb using a PFD of 12.5 MHz (R

divider=4, doubler disabled) for compatibility with

xDSL requirements, or in steps of <5.2 ppb using a

PFD of 100 MHz (R divider=1, doubler enabled) for

compatibility with broadcast video requirements. The

frequency margining features also facilitate system

design verification tests (DVT), such as standards

compliance and system timing margin testing.

–

Glitch-Less Frequency Margining: Up to ±1000

ppm From Nominal

–

Internal EEPROM: User Configurable Start-Up

Settings

•

Other Features

–

Device Control: Fast Mode I²C up to 1000 kHz

3.3-V Operating Voltage

Industrial Temperature Range (–40ºC to

+85ºC)

Device Information⁽¹⁾

–

7-mm × 5-mm 6-Pin Package

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

Default Frequency:

70.656 MHz

LMK61E08

QFM (6)

7.00 mm × 5.00 mm

–

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

2 Applications

Pinout and Simplified Block Diagram

•

High-Performance Replacement for Crystal, SAW,

or Silicon-Based Oscillators

Power

Conditioning

•

Switches, Routers, Network Line Cards, Base

Band Units (BBU), Servers, Storage/SAN

SDA

SCL

GND

VDD

Output

Divider

Output

Buffer

Integrated

Oscillator

PLL

•

Test and Measurement

Medical Imaging

OUTN

OUTP

Interface

I²C/EEPROM

FPGA, Processor Attach

xDSL, Broadcast Video

LMK61E0X

Ultra-high performance oscillator

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...54

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与LMK61E08-SIAR相关器件

型号	品牌	获取价格	描述	数据表
LMK61E08-SIAT	TI	获取价格	具有内部 EEPROM 的超低抖动可编程振荡器 \| SIA \| 6 \| -40 to 85
LMK61E0M	TI	获取价格	具有内部 EEPROM 的 LVCMOS 超低抖动可编程振荡器
LMK61E0M-SIAR	TI	获取价格	具有内部 EEPROM 的 LVCMOS 超低抖动可编程振荡器 \| SIA \| 8 \| -
LMK61E0M-SIAT	TI	获取价格	具有内部 EEPROM 的 LVCMOS 超低抖动可编程振荡器 \| SIA \| 8 \| -
LMK61E2	TI	获取价格	156.250MHz、±50ppm、超低抖动、集成式 EEPROM、完全可编程振荡器
LMK61E2-100M	TI	获取价格	100MHz、±50ppm、LVPECL 超低抖动标准差动振荡器
LMK61E2-100M00SIAR	TI	获取价格	100MHz、±50ppm、LVPECL 超低抖动标准差动振荡器 \| SIA \| 6 \|
LMK61E2-100M00SIAT	TI	获取价格	100MHz、±50ppm、LVPECL 超低抖动标准差动振荡器 \| SIA \| 6 \|
LMK61E2-125M	TI	获取价格	125MHz、±50ppm、LVPECL 超低抖动标准差动振荡器
LMK61E2-125M00SIAR	TI	获取价格	125MHz、±50ppm、LVPECL 超低抖动标准差动振荡器 \| SIA \| 6 \|

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