LMK1D2106, LMK1D2108
SNAS829 – OCTOBER 2021
LMK1D210x Low Additive Jitter LVDS Buffer
1 Features
3 Description
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High-performance LVDS clock buffer family: up to
2 GHz
The LMK1D210x clock buffer distributes two clock
inputs (IN0 and IN1) to a total of 16 pairs of
differential LVDS clock outputs (OUT0 to OUT15) in
the LMK1D2108 and 12 pairs of clock outputs (OUT0
to OUT11) in the LMK1D2106 with minimum skew
for clock distribution. Each buffer block consists of
one input and a maximum of 6 (LMK1D2106) or 8
(LMK1D2108) LVDS outputs. The inputs can either be
LVDS, LVPECL, HCSL, CML, or LVCMOS.
– Dual 1:6 differential buffer
– Dual 1:8 differential buffer
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12-
kHz to
20-MHz at 156.25 MHz
– Very low phase noise floor: -164 dBc/Hz
(typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD
typical when AMP_SEL = 1
Bank enable/disable using the EN pin
Universal inputs accept LVDS, LVPECL, LVCMOS,
HCSL and CML signal levels
LVDS reference voltage, VAC_REF, available for
capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
– LMK1D2106: 6-mm × 6-mm, 40-pin VQFN
(RHA)
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The LMK1D210x is specifically designed for driving
50-Ω transmission lines. When driving inputs in
single-ended mode, apply the appropriate bias
voltage to the unused negative input pin (see Figure
8-6).
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Using the control pin (EN), output banks can either be
enable or disabled. If this pin is left open, both bank
outputs are enabled. If the control pin is switched to a
logic "0", both bank outputs are disabled (static logic
"0"). If the control pin is switched to a logic "1", the
outputs of one bank are disabled while the outputs of
the other bank are enabled. The part also supports a
fail-safe function. The device further incorporates an
input hysteresis which prevents random oscillation of
the outputs in the absence of an input signal.
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– LMK1D2108: 7-mm × 7-mm, 48-pin VQFN
(RGZ)
The device operates in a 1.8-V, 2.5-V, or 3.3-V
supply environment and is characterized from –40°C
to 105°C (ambient temperature).
2 Applications
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Telecommunications and networking
Medical imaging
Test and measurement
Wireless infrastructure
Pro audio, video and signage
Device Information
PART NUMBER(1)
LMK1D2106
PACKAGE
VQFN (40)
VQFN (48)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
7.00 mm × 7.00 mm
LMK1D2108
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
491.52 MHz
AFE DEVICE
CLOCK
EN
LMK1D21XX
LVDS Buffer
AFE
7.68 MHz
AFE SYSREF
CLOCK
Application Example
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.