Datasheet > LMK1D2102RGTT

LMK1D2102RGTT

更新时间： 2024-11-10 02:50:55

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
33页	2052K
描述
LMK1D210x Low Additive Jitter LVDS Buffer

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LMK1D2102RGTT 数据手册

LMK1D2102, LMK1D2104

SNAS822 – SEPTEMBER 2021

LMK1D210x Low Additive Jitter LVDS Buffer

1 Features

3 Description

•

High-performance LVDS clock buffer family: up to

2 GHz

– Dual 1:2 differential buffer

The LMK1D210x clock buffer distributes two clock

inputs (IN0 and IN1) to a total of up to 8 pairs of

differential LVDS clock outputs (OUT0, OUT7) with

minimum skew for clock distribution. Each buffer block

consists of one input and up to 4 LVDS outputs. The

inputs can either be LVDS, LVPECL, HCSL, CML or

LVCMOS.

– Dual 1:4 differential buffer

•

Supply voltage: 1.71 V to 3.465 V

Low additive jitter: < max 60 fs RMS in 12-kHz to

20-MHz @ 156.25 MHz

– Very low phase noise floor: -164 dBc/Hz

(typical)

Very low propagation delay < 575 ps max

Output skew of 20 ps max

Universal inputs accept LVDS, LVPECL, LVCMOS,

HCSL and CML signal levels.

The LMK1D210x is specifically designed for driving

50-Ω transmission lines. In case of driving the inputs

in single-ended mode, the appropriate bias voltage as

shown in Figure 8-6 must be applied to the unused

negative input pin.

•

Using the control pin (EN), output banks can either

be enabled or disabled. If this pin is left open, two

buffers with all outputs are enabled, if switched to

a logic "0", both banks with all outputs are disabled

(static logic "0"), if switched to a logic "1", one bank

and its outputs are disabled while another bank with

its outputs are enabled. The part supports a fail-safe

function. The device further incorporates an input

hysteresis which prevents random oscillation of the

outputs in the absence of an input signal.

•

LVDS reference voltage, V_{AC_REF}, available for

capacitive coupled inputs

Industrial temperature range: –40°C to 105°C

Packaged in

– LMK1D2102: 3-mm x 3-mm, 16-Pin VQFN

– LMK1D2104: 5-mm x 5-mm, 28-Pin VQFN

•

2 Applications

•

Telecommunications and networking

Medical imaging

Test and measurement

Wireless infrastructure

Pro audio, video and signage

The device operates in 1.8-V or 2.5-V or 3.3-V

supply environment and is characterized from –40°C

to 105°C (ambient temperature). The LMK1D210x

package variant is shown in the table below:

Device Information

PART NUMBER⁽¹⁾

LMK1D2102

PACKAGE

VQFN (16)

VQFN (28)

BODY SIZE (NOM)

3.00 mm × 3.00 mm

5.00 mm × 5.00 mm

LMK1D2104

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

491.52 MHz

AFE DEVICE

CLOCK

LMK1D21XX

LVDS Buffer

AFE

7.68 MHz

AFE SYSREF

CLOCK

Application Example

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...33

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与LMK1D2102RGTT相关器件

型号	品牌	获取价格	描述	数据表
LMK1D2104	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D2104RHDR	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D2104RHDT	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D2106	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D2106RHAR	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D2106RHAT	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D2108	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D2108RGZR	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D2108RGZT	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer
LMK1D210X	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer

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