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LMK1D1212 PDF预览

LMK1D1212

更新时间: 2024-01-03 07:52:45
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
36页 3404K
描述
LMK1D121x Low Additive Jitter LVDS Buffer

LMK1D1212 数据手册

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LMK1D1212, LMK1D1216  
SNAS823 – OCTOBER 2021  
LMK1D121x Low Additive Jitter LVDS Buffer  
1 Features  
3 Description  
High-performance LVDS clock buffer family: up to  
2 GHz  
The LMK1D1212 clock buffer distributes with  
minimum skew one of two selectable clock inputs  
(IN0, IN1) to 12 pairs of differential LVDS clock  
outputs (OUT0 through OUT11). Similarly, the  
LMK1D1216 distributes 16 pairs of differential  
LVDS clock outputs (OUT0 through OUT15). The  
LMK1D121x family can accept two clock sources into  
an input multiplexer. The inputs can either be LVDS,  
LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.  
– 2:12 differential buffer (LMK1D1212)  
– 2:16 differential buffer (LMK1D1216)  
Supply voltage: 1.71 V to 3.465 V  
Low additive jitter: < 60 fs RMS maximum in 12-  
kHz to  
20-MHz at 156.25 MHz  
– Very low phase noise floor: -164 dBc/Hz  
(typical)  
Very low propagation delay: < 575 ps maximum  
Output skew: 20 ps maximum  
High-swing LVDS (boosted mode): 500-mV VOD  
typical when AMP_SEL = 1  
Universal inputs accept LVDS, LVPECL, LVCMOS,  
HCSL and CML signal levels  
LVDS reference voltage, VAC_REF, available for  
capacitive-coupled inputs  
Industrial temperature range: –40°C to 105°C  
Packaged in  
The LMK1D121x is specifically designed for driving  
50-Ω transmission lines. When driving inputs in  
single-ended mode, apply the appropriate bias  
voltage to the unused negative input pin (see Figure  
8-6).  
The IN_SEL pin selects the input which is routed  
to the outputs. If this pin is left open, it disables  
the outputs (static low). The part supports a fail-safe  
function. The device further incorporates an input  
hysteresis which prevents random oscillation of the  
outputs in the absence of an input signal.  
– LMK1D1212: 6-mm × 6-mm, 40-pin VQFN  
(RHA)  
– LMK1D1216: 7-mm × 7-mm, 48-pin VQFN  
(RGZ)  
The device operates in 1.8-V or 2.5-V or 3.3-V  
supply environment and is characterized from –40°C  
to 105°C (ambient temperature).  
2 Applications  
Device Information  
PART NUMBER(1)  
LMK1D1212  
PACKAGE  
VQFN (40)  
VQFN (48)  
BODY SIZE (NOM)  
6.00 mm × 6.00 mm  
7.00 mm × 7.00 mm  
Telecommunications and networking  
Medical imaging  
Test and measurement  
Wireless infrastructure  
Pro audio, video and signage  
LMK1D1216  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
ADC CLOCK  
500 MHz  
156.25 MHz  
Oscillator  
LMK1D12XX  
LVDS Buffer  
IN_SEL  
FPGA CLOCK  
Application Example  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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