Datasheet > LMK1D1208RHDR

LMK1D1208RHDR

更新时间： 2024-11-08 02:50:47

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
35页	1981K
描述
LMK1D120x Low Additive Jitter LVDS Buffer

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LMK1D1208RHDR 数据手册

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

LMK1D120x Low Additive Jitter LVDS Buffer

1 Features

3 Description

•

High-performance LVDS clock buffer family with 2

inputs and 4 (2:4) or 8 (2:8) outputs.

Output frequency up to 2 GHz.

Supply voltage: 1.71 V to 3.465 V

Low additive jitter: < maximum 60 fs RMS in 12-

kHz to 20-MHz at 156.25 MHz

– Very low phase noise floor: –164 dBc/Hz

(typical)

Very low propagation delay: < 575 ps maximum

Output skew: 20 ps maximum

Universal inputs accept LVDS, LVPECL, LVCMOS,

LP-HCSL, HCSL and CML inputs

LVDS reference voltage, V_{AC_REF}, available for

capacitive-coupled inputs

Industrial temperature range: –40°C to 105°C

Packages available:

– LMK1D1204: 3-mm × 3-mm, 16-pin VQFN

(RGT)

– LMK1D1208: 5-mm × 5-mm, 28-pin VQFN

(RHD)

The LMK1D120x clock buffer distributes one of two

selectable clock inputs (IN0 and IN1) to 4 or 8 pairs

of differential LVDS clock outputs (OUT0 through

OUT7) with minimum skew for clock distribution. The

LMK1D12x family can accept two clock sources into

an input multiplexer. The inputs can either be LVDS,

LVPECL, LP-HCSL, HCSL, CML or LVCMOS.

•

The LMK1D12x is specifically designed for driving 50-

Ω transmission lines. In case of driving the inputs in

single-ended mode, the appropriate bias voltage as

shown in Figure 8-6 must be applied to the unused

negative input pin.

•

The IN_SEL pin selects the input which is routed

to the outputs. If this pin is left open, it disables

the outputs (logic low). The part supports a fail-safe

function. The device further incorporates an input

hysteresis which prevents random oscillation of the

outputs in the absence of an input signal.

•

The device operates in 1.8-V or 2.5-V or 3.3-V

supply environment and is characterized from –40°C

to 105°C (ambient temperature). The LMK1D12x

package variant is shown in the table below:

2 Applications

•

Telecommunications and networking

Medical imaging

Test and measurement

Wireless infrastructure

Pro audio, video and signage

Device Information

PART NUMBER⁽¹⁾

LMK1D1204

PACKAGE

VQFN (16)

VQFN (28)

BODY SIZE (NOM)

3.00 mm × 3.00 mm

5.00 mm × 5.00 mm

LMK1D1208

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

ADC CLOCK

F1 MHz

100 Ω

156.25 MHz

Oscillator

LMK1D 12XX

LVDS Buffer

IN_SEL

FPGA CLOCK

100 Ω

Application Example

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...35

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与LMK1D1208RHDR相关器件

型号	品牌	获取价格	描述	数据表
LMK1D1208RHDT	TI	获取价格	LMK1D120x Low Additive Jitter LVDS Buffer
LMK1D120X	TI	获取价格	LMK1D120x Low Additive Jitter LVDS Buffer
LMK1D1212	TI	获取价格	LMK1D121x Low Additive Jitter LVDS Buffer
LMK1D1212RHAR	TI	获取价格	LMK1D121x Low Additive Jitter LVDS Buffer
LMK1D1212RHAT	TI	获取价格	LMK1D121x Low Additive Jitter LVDS Buffer
LMK1D1216	TI	获取价格	LMK1D121x Low Additive Jitter LVDS Buffer
LMK1D1216RGZR	TI	获取价格	LMK1D121x Low Additive Jitter LVDS Buffer
LMK1D1216RGZT	TI	获取价格	LMK1D121x Low Additive Jitter LVDS Buffer
LMK1D121X	TI	获取价格	LMK1D121x Low Additive Jitter LVDS Buffer
LMK1D2102	TI	获取价格	LMK1D210x Low Additive Jitter LVDS Buffer

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