5秒后页面跳转
LMH2180YD PDF预览

LMH2180YD

更新时间: 2024-11-18 03:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟驱动器逻辑集成电路
页数 文件大小 规格书
16页 503K
描述
75 MHz Dual Clock Buffer

LMH2180YD 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:LLP-8Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.33
Is Samacsys:N系列:2180
输入调节:STANDARDJESD-30 代码:S-XDSO-N8
JESD-609代码:e1长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:2反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVSON
封装等效代码:SOLCC8,.11,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE电源:2.5/5 V
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:Clock Drivers最大供电电压 (Vsup):5 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL宽度:3 mm
最小 fmax:75 MHzBase Number Matches:1

LMH2180YD 数据手册

 浏览型号LMH2180YD的Datasheet PDF文件第2页浏览型号LMH2180YD的Datasheet PDF文件第3页浏览型号LMH2180YD的Datasheet PDF文件第4页浏览型号LMH2180YD的Datasheet PDF文件第5页浏览型号LMH2180YD的Datasheet PDF文件第6页浏览型号LMH2180YD的Datasheet PDF文件第7页 
January 24, 2008  
LMH2180  
75 MHz Dual Clock Buffer  
General Description  
The LMH2180 is a high speed dual clock buffer designed for  
portable communications and applications requiring multiple  
accurate multi-clock systems. The LMH2180 integrates two  
75 MHz low noise buffers with independent shutdown pins  
into a small package. The LMH2180 ensures superb system  
operation between the baseband and the oscillator signal  
path by eliminating crosstalk between the multiple clock sig-  
nals.  
Features  
(Typical values are: VSUPPLY = 2.7V and CL = 10 pF, unless  
otherwise specified.)  
Small signal bandwidth  
Supply voltage range  
Phase noise (VIN = 1 VPP  
78 MHz  
2.4V to 5V  
-123dBc/Hz  
,
fC = 38.4 MHz, Δf = 1kHz)  
Slew rate  
106 V/μs  
2.3 mA  
30 µA  
Total supply current  
Unique technology and design provides the LMH2180 with  
the ability to accurately drive both large capacitive and resis-  
tive loads. Low supply current combined with shutdown pins  
for each channel means the LMH2180 is ideal for battery  
powered applications. The LMH2180's rapid recovery after  
disable optimizes performance and current consumption.  
This part does not use an internal ground reference, thus pro-  
viding additional system flexibility. The LMH2180 operates  
both with single and split supplies.  
Shutdown current  
Rail-to-rail input and output  
Individual buffer enable pins  
Rapid Ton technology  
Crosstalk rejection circuitry  
8-pin LLP, pin access packaging  
Temperature range  
−40°C to 85°C  
The flexible buffers provide system designers the capacity to  
manage complex clock signals in the latest wireless applica-  
tions. Each buffer delivers 106 V/μs internal slew rate with  
independent shutdown and duty cycle precision. The patent-  
ed analog circuit of each buffer drives capacitive loads greater  
than 20 pF. Each input is internally biased to 1V, removing  
the need for external resistors. Both channels have rail-to-rail  
inputs and outputs, a gain of one, and are AC coupled with  
the use of one capacitor.  
Applications  
3G mobile applications  
WLAN–WiMAX modules  
TD_SCDMA multi-mode MP3 and camera  
GSM modules  
Oscillator modules  
Replacing a discrete buffer solution with the LMH2180 pro-  
vides many benefits: simplified board layout, minimized par-  
asitic components, simplified BOM, design durability across  
multiple applications, simplification of clock paths, and the  
ability to reduce the number of clock signal generators in the  
system. The LMH2180 is produced in the tiny 8-pin LLP solder  
bump and no pullback packages minimizing the required PCB  
space. National’s advanced packaging offers direct PCB-IC  
evaluation via pin access.  
Typical Application  
30024602  
© 2008 National Semiconductor Corporation  
300246  
www.national.com  

与LMH2180YD相关器件

型号 品牌 获取价格 描述 数据表
LMH2180YD/NOPB TI

获取价格

75 MHz Dual Clock Buffer 8-WSON -40 to 85
LMH2180YDX NSC

获取价格

75 MHz Dual Clock Buffer
LMH2180YDX TI

获取价格

LMH2180 75 MHz Dual Clock Buffer
LMH2180YDX/NOPB TI

获取价格

75 MHz Dual Clock Buffer 8-WSON -40 to 85
LMH2190 NSC

获取价格

Quad Channel 27 MHz Clock Tree Driver with I2C Interface
LMH2190 TI

获取价格

具有 I2C 接口的四通道 27MHz 时钟树驱动器
LMH2190TM-38 NSC

获取价格

Quad Channel 27 MHz Clock Tree Driver with I2C Interface
LMH2190TM-38/NOPB TI

获取价格

具有 I2C 接口的四通道 27MHz 时钟树驱动器 | YFQ | 16 | -20 t
LMH2190TMX-38 NSC

获取价格

Quad Channel 27 MHz Clock Tree Driver with I2C Interface
LMH2191 NSC

获取价格

Evaluation Board for the Dual Channel 52 MHz Clock Tree Driver