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LMH2180SDE PDF预览

LMH2180SDE

更新时间: 2024-11-18 19:51:51
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动输出元件逻辑集成电路
页数 文件大小 规格书
16页 446K
描述
IC 2180 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), DSO8, LLP-8, Clock Driver

LMH2180SDE 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:HVSON, SOLCC8,.11,20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.15
Is Samacsys:N系列:2180
输入调节:STANDARDJESD-30 代码:S-XDSO-N8
JESD-609代码:e0长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:2
反相输出次数:端子数量:8
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVSON封装等效代码:SOLCC8,.11,20
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5/5 V
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:Clock Drivers最大供电电压 (Vsup):5 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm最小 fmax:75 MHz
Base Number Matches:1

LMH2180SDE 数据手册

 浏览型号LMH2180SDE的Datasheet PDF文件第2页浏览型号LMH2180SDE的Datasheet PDF文件第3页浏览型号LMH2180SDE的Datasheet PDF文件第4页浏览型号LMH2180SDE的Datasheet PDF文件第5页浏览型号LMH2180SDE的Datasheet PDF文件第6页浏览型号LMH2180SDE的Datasheet PDF文件第7页 
August 21, 2008  
LMH2180  
75 MHz Dual Clock Buffer  
General Description  
The LMH2180 is a high speed dual clock buffer designed for  
portable communications and applications requiring multiple  
accurate multi-clock systems. The LMH2180 integrates two  
75 MHz low noise buffers with independent shutdown pins  
into a small package. The LMH2180 ensures superb system  
operation between the baseband and the oscillator signal  
path by eliminating crosstalk between the multiple clock sig-  
nals.  
Features  
(Typical values are: VSUPPLY = 2.7V and CL = 10 pF, unless  
otherwise specified.)  
Small signal bandwidth  
Supply voltage range  
Phase noise (VIN = 1 VPP  
78 MHz  
2.4V to 5V  
,
−123 dBc/Hz  
fC = 38.4 MHz, Δf = 1 kHz)  
Slew rate  
Total supply current  
106 V/μs  
2.3 mA  
30 µA  
Unique technology and design provides the LMH2180 with  
the ability to accurately drive both large capacitive and resis-  
tive loads. Low supply current combined with shutdown pins  
for each channel means the LMH2180 is ideal for battery  
powered applications. This part does not use an internal  
ground reference, thus providing additional system flexibility.  
Shutdown current  
Rail-to-rail input and output  
Individual buffer enable pins  
Rapid Ton technology  
Crosstalk rejection circuitry  
Packages:  
The flexible buffers provide system designers the capacity to  
manage complex clock signals in the latest wireless applica-  
tions. Each buffer delivers 106 V/μs internal slew rate with  
independent shutdown and duty cycle precision. Each input  
is internally biased to 1V, removing the need for external re-  
sistors. Both channels have rail-to-rail inputs and outputs, a  
gain of one, and are AC coupled with the use of one capacitor.  
8-Pin LLP, Solder Bump and no Pullback  
8-Bump micro SMD  
Temperature range  
−40°C to 85°C  
Applications  
3G mobile applications  
Replacing a discrete buffer solution with the LMH2180 pro-  
vides many benefits: simplified board layout, minimized par-  
asitic components, simplified BOM, design durability across  
multiple applications, simplification of clock paths, and the  
ability to reduce the number of clock signal generators in the  
system. The LMH2180 is produced in the tiny packages min-  
imizing the required PCB space.  
WLAN–WiMAX modules  
TD_SCDMA multi-mode MP3 and camera  
GSM modules  
Oscillator modules  
Typical Application  
30024602  
© 2008 National Semiconductor Corporation  
300246  
www.national.com  

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