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LMH0071SQE PDF预览

LMH0071SQE

更新时间: 2024-01-14 05:11:32
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
28页 543K
描述
3 Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface

LMH0071SQE 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:HVQCCN,
Reach Compliance Code:compliant风险等级:5.67
差分输出:YES输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:GENERAL PURPOSE
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:7 mm湿度敏感等级:3
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260最大接收延迟:
接收器位数:5座面最大高度:0.8 mm
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V电源电压1-最大:3.465 V
电源电压1-分钟:3.135 V电源电压1-Nom:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

LMH0071SQE 数据手册

 浏览型号LMH0071SQE的Datasheet PDF文件第2页浏览型号LMH0071SQE的Datasheet PDF文件第3页浏览型号LMH0071SQE的Datasheet PDF文件第4页浏览型号LMH0071SQE的Datasheet PDF文件第5页浏览型号LMH0071SQE的Datasheet PDF文件第6页浏览型号LMH0071SQE的Datasheet PDF文件第7页 
October 5, 2009  
LMH0341, LMH0041,  
LMH0071, LMH0051  
3 Gbps, HD, SD, DVB-ASI SDI Deserializer with  
Loopthrough and LVDS Interface  
General Description  
Key Specifications  
The LMH0341/0041/0071/0051 SDI Deserializers are part of  
National’s family of FPGA-Attach SER/DES products sup-  
porting 5-bit LVDS interfaces with FPGAs. When paired with  
a host FPGA the LMH0341 automatically detects the incom-  
ing data rate and decodes the raw 5-bit data words compliant  
to any of the following standards: DVB-ASI, SMPTE 259M,  
SMPTE 292M, or SMPTE 424M. See Table 1 for details on  
which Standards are supported per device.  
Output compliant with SMPTE 259M-C, SMPTE 292M,  
SMPTE 424M and DVB-ASI (See Table 1)  
Typical power dissipation: 590 mW (loopthrough disabled,  
3G datarate)  
0.6 UI Minimum Input Jitter Tolerance  
Features  
5–bit LVDS Interface  
The interface between the LMH0341 and the host FPGA con-  
sists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus  
interface. No external VCOs or clocks are required. The  
LMH0341 CDR detects the frequency from the incoming data  
stream, generates a clean clock and transmits both clock and  
data to the host FPGA. The LMH0341, LMH0041 and  
LMH0071 include a serial reclocked loopthrough with inte-  
grated SMPTE compliant cable driver. Refer to table 1 for a  
complete listing of single channel deserializers offered in this  
family.  
No external VCO or clock required  
Reclocked serial loopthrough with Cable Driver  
Powerdown Mode  
3.3V SMBus configuration interface  
Small 48 pin LLP package  
Industrial Temperature range:-40°C to +85°C  
Applications  
The FPGA-Attach SER/DES product family is supported by a  
suite of IP which allows the design engineer to quickly develop  
video applications using the SER/DES products. The product  
is packaged in a physically small 48 pin LLP package.  
SDI interfaces for:  
Video Cameras  
DVRs  
Video Switchers  
Video Editing Systems  
General Block Diagram  
30017201  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2009 National Semiconductor Corporation  
300172  
www.national.com  

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