January 2006
LMH0031
SMPTE 292M/259M Digital Video Deserializer /
Descrambler with Video and Ancillary Data FIFOs
The LMH0031’s internal circuitry is powered from +2.5 Volts
and the I/O circuitry from a +3.3 Volt supply. Power dissipa-
tion is typically 850mW. The device is packaged in a 64-pin
TQFP.
General Description
The LMH0031 SMPTE 292M
/ 259M Digital Video
Deserializer/Descrambler with Video and Ancillary Data
FIFOs is a monolithic integrated circuit that deserializes and
decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial
component video data, to 20-bit parallel data with a synchro-
nized parallel word-rate clock. It also deserializes and de-
Features
n SDTV/HDTV serial digital video standard compliant
n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps
and 1.485 Gbps serial video data rates with
auto-detection
codes
SMPTE
259M,
270Mbps,
360Mbps
and
SMPTE 344M (proposed) 540Mbps serial component video
data, to 10-bit parallel data. Functions performed by the
LMH0031 include: clock/data recovery from the serial data,
serial-to-parallel data conversion, SMPTE standard data de-
coding, NRZI-to-NRZ conversion, parallel data clock genera-
tion, word framing, CRC and EDH data checking and han-
dling, Ancillary Data extraction and automatic video format
determination. The parallel video output features a variable-
depth FIFO which can be adjusted to delay the output data
up to 4 parallel data clock periods. Ancillary Data may be
selectively extracted from the parallel data through the use
of masking and control bits in the configuration and control
registers and stored in the on-chip FIFO. Reverse LSB dith-
ering is also implemented.
n LSB de-dithering option
n Uses low-cost 27MHz crystal or clock oscillator
reference
<
n Fast VCO lock time: 500 µs at 1.485 Gbps
n Built-in self-test (BIST) and video test pattern generator
(TPG)*
n Automatic EDH/CRC word and flag processing
n Ancillary Data FIFO with extensive packet handling
options
n Adjustable, 4-deep parallel output video data FIFO
n Flexible control and configuration I/O port
n LVCMOS compatible control inputs and clock and data
outputs
n LVDS and ECL-compatible, differential, serial inputs
n 3.3V I/O power supply and 2.5V logic power supply
operation
The unique multi-functional I/O port of the LMH0031 pro-
vides external access to functions and data stored in the
configuration and control registers. This feature allows the
designer greater flexibility in tailoring the LMH0031 to the
desired application. The LMH0031 is auto-configured to a
default operating condition at power-on or after a reset com-
mand. Separate power pins for the PLL, deserializer and
other functional circuits improve power supply rejection and
noise performance.
n Low power: typically 850mW
n 64-pin TQFP package
n Commercial temperature range 0˚C to +70˚C
* Patent applications made or pending.
The LMH0031 has a unique Built-In Self-Test (BIST) and
video Test Pattern Generator (TPG). The BIST enables com-
prehensive testing of the device by the user. The BIST uses
the TPG as input data and includes SD and HD component
video test patterns, reference black, PLL and EQ pathologi-
cals and a 75% saturation, 8 vertical colour bar pattern, for
all implemented rasters. The colour bar pattern has optional
transition coding at changes in the chroma and luma bar
data. The TPG data is output via the parallel data port.
Applications
n SDTV/HDTV serial-to-parallel digital video interfaces for:
— Video editing equipment
— VTRs
— Standards converters
— Digital video routers and switchers
— Digital video processing and editing equipment
— Video test pattern generators and digital video test
equipment
The LMH0030, SMPTE 292M / 259M Digital Video Serializer
with Ancillary Data FIFO and Integrated Cable Driver, is the
ideal complement to the LMH0031.
— Video signal generators
Ordering Information
Order Number
Package Type
64-Pin TQFP
NS Package Number
LMH0031VS
VEC-64A
© 2006 National Semiconductor Corporation
DS201796
www.national.com
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