LMA1010/2010
DEVICES INCORPORATED
16 x 16-bit Multiplier-Accumulator
LMA1010/2010
16 x 16-bit Multiplier-Accumulator
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The LMA1010 and LMA2010 are TC, ACC, and SUB controls are latched
high-speed, low power 16-bit on the rising edge of the logical OR of
multiplier-accumulators. The LMA1010 CLK A and CLK B. TC specifies the
and LMA2010 are functionally identical; input as two’s complement
❑ 20 ns Multiply-Accumulate Time
❑ Replaces Fairchild TMC2210,
Cypress CY7C510, IDT 7210L,
and AMD Am29510
they differ only in packaging. Full mili- (TC HIGH) or unsigned magnitude
tary ambient temperature range opera- (TC LOW). RND, when HIGH, adds ‘1’
tion is achieved with advanced CMOS to the most significant bit position of
❑ Two’s Complement or Unsigned
Operands
❑ Accumulator Performs Preload,
technology.
the least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit preci-
sion.
Accumulate, and Subtract
The LMA1010 and LMA2010 produce
the 32-bit product of two 16-bit numbers.
The results of a series of multiplications
may be accumulated to form the sum of
❑ Three-State Outputs
❑ 68-pinPLCC, J-Lead
products. Accumulation is performed to ACC and SUB control accumulator
35-bitprecisionwiththemultiplierprod- operation. ACC HIGH results in
uct sign extended as appropriate.
addition of the multiplier product and
the accumulator contents, with the result
stored in the accumulator register on the
rising edge of CLK R. ACC and SUB
HIGH results in subtraction of the
accumulator contents from the
multiplierproduct,withtheresult stored
in the accumulator register. With ACC
LOW and SUB LOW, no accumulation
occurs and the next product is loaded
directly into the accumulator register.
ACC LOW and SUB HIGH is undefined.
Data present at the A and B input regis-
ters is latched on the rising edges of
CLK A and CLK B respectively. RND,
LMA1010/2010 BLOCK DIAGRAM
B
R
15-0
15-0
A
15-0
16
16
CLK A
CLK B
A REGISTER
B REGISTER
The LMA1010/2010 output register
(accumulator register) is divided into
three independently controlled sec-
tions. The least significant result
(LSR) and most significant result
(MSR) registers are 16 bits in length.
The extended result register (XTR) is
3 bits long. The output signals R15-0
and input signals B15-0 share the same
bidirectional pins.
RND
TC
ACC
SUB
32
R
R + A
R – A
A
OEX
LEX
LEM
LEL
35
PASS R
PRELOAD
CONTROL
LOGIC
OEM
OEL
3
PREL
Each output register has an indepen-
dent output enable control. In addition
to providing three-state control of the
outputbuffers, whenOEX, OEM, orOEL
areHIGHandPRELisHIGH,datacanbe
preloaded via the bidirectional output
pins into the respective output registers.
Data present on the output pins is
latched onthe rising edge of CLK R. The
interrelation of PREL and the enable
controls is summarized in Table 1.
3
OEX
OEM
OEL
LEX
35
LEM
LEL
3
16
16
CLK R
ACCUMULATOR REGISTER
OEX
OEM
16
OEL
16
3
R
34-32
R31-16
Multiplier-Accumulators
08/16/2000–LDS.10/2010-P
1