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LM98725
SNAS474H –APRIL 2009–REVISED MARCH 2015
LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output,
Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation
1 Features
3 Description
The LM98725 is a fully integrated, high performance
16-Bit, 81 MSPS signal processing solution for digital
color copiers, scanners, and other image processing
applications. The LM98725 achieves high-speed
signal throughput with an innovative architecture
utilizing Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold
(S/H) inputs (for higher speed CCD or CMOS image
sensors). The signal paths utilize 8 bit Programmable
Gain Amplifiers (PGA), a ±9-Bit offset correction
DAC, and independently controlled Digital Black
Level correction loops for each input. The
independently programmed PGA and offset DAC
allow unique values of gain and offset for each of the
three analog inputs. The signals are then routed to a
81 MHz high performance analog-to-digital converter
(ADC). The fully differential processing channel
shows exceptional noise immunity with a very low
noise floor of –74 dB. The 16-bit ADC has excellent
dynamic performance making the LM98725
transparent in the image reproduction chain.
1
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LVDS/CMOS Outputs
LVDS/CMOS/Crystal Clock Source with PLL
Multiplication
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Integrated Flexible Spread Spectrum Clock
Generation
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CDS or S/H Processing for CCD or CIS Sensors
Independent Gain/Offset Correction for Each
Channel
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Automatic per-Channel Gain and Offset
Calibration
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Programmable Input Clamp Voltage
Flexible CCD/CIS Sensor Timing Generator
2 Applications
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Multi-Function Peripherals
High-speed Currency/Check Scanners
Flatbed or Handheld Color Scanners
High-speed Document Scanners
Key Specifications:
A very flexible integrated Spread Spectrum Clock
Generation (SSCG) modulator is included to assist
with EM compliance and reduce system costs.
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Maximum Input Level
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1.2 or 2.4 Volt Modes
Device Information(1)
(Both with + or - Polarity Option)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
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ADC Resolution: 16-Bit
LM98725
TSSOP (56)
14.0 mm × 6.10 mm
ADC Sampling Rate: 81 MSPS
INL: +17/- 28 LSB (typ)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Channel Sampling Rate: 30/30/27 MSPS
PGA Gain Steps: 256 Steps
System Block Diagram
CCD/CIS Sensor
PGA Gain Range: 0.62 to 8.3x
Analog DAC Resolution: ±9 Bits
Analog DAC Range: ±307 mV or ±614 mV
Digital DAC Resolution: ±6 Bits
Digital DAC Range: -2048 LSB to + 2016 LSB
SNR: –74dB (@0 dB PGA Gain)
Power Dissipation: 755 mW (LVDS)
Operating Temp: 0 to 70°C
Analog Front End
SPI
Image Processor/
LM98725
ASIC
Data Output
CCD Timing
Sensor Drivers
Generator
Motor
Controllers
CLK
SSCG
Supply Voltage: 3.3 V Nominal (3.0-V to 3.6-V
Range)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.