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LM5115A PDF预览

LM5115A

更新时间: 2024-11-16 04:20:07
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器稳压器
页数 文件大小 规格书
20页 403K
描述
Secondary Side Post Regulator/DC-DC Converter with Power-up/Power-down Tracking

LM5115A 数据手册

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January 2007  
LM5115A  
Secondary Side Post Regulator/DC-DC Converter with  
Power-up/Power-down Tracking  
General Description  
Features  
The LM5115A controller contains all of the features neces-  
sary to produce multiple tracking outputs using the Secondary  
Side Post Regulation (SSPR) technique. The SSPR tech-  
nique develops a highly efficient and well regulated auxiliary  
output from the secondary side switching waveform of an iso-  
lated power converter. LM5115A can be also used as a  
standalone DC/DC synchronous buck controller (Refer to  
Synchronous Buck section). Regulation of the auxiliary  
output voltage is achieved by leading edge pulse width mod-  
ulation (PWM) of the main channel duty cycle. Leading edge  
modulation is compatible with either current mode or voltage  
mode control of the main output. The LM5115A drives exter-  
nal high-side and low-side NMOS power switches configured  
as a synchronous buck regulator. A current sense amplifier  
provides overload protection and operates over a wide com-  
mon mode input range. Additional features include a low  
dropout (LDO) bias regulator, error amplifier, precision refer-  
ence, adaptive dead time control of the gate signals and  
thermal shutdown.  
Power-up/Power-down Tracking  
Self-synchronization to main channel output  
Leading edge pulse width modulation  
Valley current Mode control  
Standalone DC/DC synchronous buck mode  
Operates from AC or DC input up to 75V  
Wide 4.5V to 30V bias supply range  
Wide 0.75V to 13.5V output range.  
Top and bottom gate drivers sink 2.5A peak  
Adaptive gate driver dead-time control  
Wide bandwidth error amplifier (4MHz)  
Programmable soft-start  
Thermal shutdown protection  
TSSOP-16 package  
Typical Application Circuit  
20207101  
FIGURE 1. Simplified Multiple Output Power Converter Utilizing SSPR Technique  
© 2007 National Semiconductor Corporation  
202071  
www.national.com  

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