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LM317T PDF预览

LM317T

更新时间: 2024-10-29 20:20:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 局域网输出元件调节器
页数 文件大小 规格书
7页 117K
描述
Adjustable Positive Standard Regulator, 1.2V Min, 37V Max, BIPolar, PSFM3, PLASTIC, TO-220, 3 PIN

LM317T 技术参数

生命周期:Transferred零件包装代码:SFM
包装说明:TO-220, SIP3,.1TB针数:3
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.27
可调性:ADJUSTABLE标称回动电压 1:3 V
最大差分输入-输出电压:40 V最小差分输入-输出电压:3 V
JESD-30 代码:R-PSFM-T3JESD-609代码:e0
最大电网调整率 (%/V):0.07最大负载调整率 (%):1.5%
功能数量:1输出次数:1
端子数量:3工作温度TJ-Max:125 °C
工作温度TJ-Min:-40 °C最大输出电流 1:1.5 A
最大输出电压 1:37 V最小输出电压 1:1.2 V
封装主体材料:PLASTIC/EPOXY封装代码:TO-220
封装等效代码:SIP3,.1TB封装形状:RECTANGULAR
封装形式:FLANGE MOUNT认证状态:Not Qualified
调节器类型:ADJUSTABLE POSITIVE SINGLE OUTPUT STANDARD REGULATOR子类别:Other Regulators
表面贴装:NO技术:BIPOLAR
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:SINGLE

LM317T 数据手册

 浏览型号LM317T的Datasheet PDF文件第2页浏览型号LM317T的Datasheet PDF文件第3页浏览型号LM317T的Datasheet PDF文件第4页浏览型号LM317T的Datasheet PDF文件第5页浏览型号LM317T的Datasheet PDF文件第6页浏览型号LM317T的Datasheet PDF文件第7页 
Order this document  
by MCM6726D/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6726D  
128K x 8 Bit Fast Static Random  
Access Memory  
The MCM6726D is a 1,048,576 bit static random access memory organized  
as 131,072 words of 8 bits. Static design eliminates the need for external clocks  
or timing strobes.  
Output enable (G) is a special control feature that provides increased system  
flexibility and eliminates bus contention problems.  
WJ PACKAGE  
400 MIL SOJ  
CASE 857A–02  
This device meets JEDEC standards for functionality and revolutionary pinout,  
and is available in a 400 mil plastic small–outline J–leaded package.  
PIN ASSIGNMENT  
Single 5 V ± 10% Power Supply  
A
A
A
1
32  
31  
30  
29  
28  
27  
Fully Static — No Clock or Timing Strobes Necessary  
All Inputs and Outputs Are TTL Compatible  
Three State Outputs  
Fast Access Times: 8, 10, 12 ns  
Center Power and I/O Pins for Reduced Noise  
A
2
A
A
3
A
A
4
G
E
5
DQ  
DQ  
DQ  
DQ  
V
6
7
26  
25  
24  
23  
22  
21  
20  
BLOCK DIAGRAM  
V
8
SS  
CC  
A
A
A
V
V
9
SS  
CC  
V
V
CC  
SS  
DQ  
DQ  
DQ  
A
10  
11  
12  
13  
14  
DQ  
W
A
A
MEMORY  
ROW  
DECODER  
MATRIX  
512 ROWS x 256 x 8  
COLUMNS  
A
A
A
A
A
A
A
A
A
A
A
A
19  
18  
17  
15  
16  
DQ  
COLUMN I/O  
PIN NAMES  
INPUT  
DATA  
CONTROL  
COLUMN DECODER  
A . . . . . . . . . . . . . . . . . . . . Address Input  
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
DQ . . . . . . . . . . . . . . . Data Input/Output  
DQ  
A
A
A
A
A
A
A
A
V
CC  
V
SS  
. . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
E
W
G
10/9/96  
Motorola, Inc. 1996  

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